4 channel ADC, 10 MHz, 8 bit design

[FrankBuss]

I'm planning to build a 4 channel ADC shield, for the Microsemi Creative FPGA board, which has Arduino compatible headers (with 3.3 V for the digital IOs). I would like to sample +/-10 V with 10 MHz samplerate. No need for gain etc., I plan to use it to record the programming sequence of a microcontroller programmer. With the integrated RAM on the Creative board I can sample 64 MB, so more than a second for 8 bit resolution and 10 MHz samplerate, and then I can transfer it over UART to a PC. I don't need more at the moment.

Attached is a first draft of the circuit diagram, with one input stage and one ADC. It is mainly copied from the application notes from the datasheets, except for the ADA4622, which I'm planning to use for the input stage. Is this sufficient for a few MHz analog bandwidth and does the rest look good? I'm not sure about the input range and if U2 does the right voltage shifting, I have no idea how a current feedback OpAmp works. Calibration etc. is no problem, I will do this in software.

[Kleinstein]

It  don't think U2 will do much level shifting. It's essentially a differential amplifier with a little gain (e.g. 1.5 times).  R12 and R18 should be likely swapped. I would expect some limiting here - chance are U2 would also give out negative voltages. Level shifting would need some kind of DC reference level (possibly derived from the reference).

There is no real need for R9, unless there is a longer coax line between U4A and R9.

The LMC662 for the reference buffer is an odd choice. Q2 is also the wrong way around.

The input divider with R1,R3 would need an additional adjustable (trimmer) capacitive divider in parallel to get some compensation.

For better channel separation and less concentrated heat I would not use the ADA4622-4 but more like 4 separate chips.

[FrankBuss]

Thanks for the review. The LMC662 is from the datasheet example of the ADC: https://www.ti.com/lit/ds/symlink/adc1175.pdf see page 18. Why is it an odd choice?

The LMH6702 is also in the datasheet as an example on page 16. But I guess they assume only positive input then? How do I need to change it to allow positive and negative input?

Do you have an example for the additional capacitive divider for R1, R3?

Good idea with the ADA4622, I will change it to 4 separate ADA4622-1 ICs.

[David Hess]

Your VRB generator circuit is well thought out but the PNP transistor is reversed.  The reference circuits may need a higher minimum load for stability than the reference inputs of the ADCs will provide.

U2 is configured as a non-inverting amplifier and not level shifting anything so that needs to be changed.  Usually the singled ended reference to the ADC is divided by 2 and fed to the level shifter to move the signal up by half of the ADC input range but that will not work here.  It may be easier to use an ADC which has a bipolar input range simplifying the reference but a level shifter can be made to work.

The high input impedance divider is going to require frequency compensation to maintain the same attenuation at higher frequencies.  A small fixed capacitor across R1 and a trimmer capacitor R3 (or the reverse) will work; calibrate with a square wave test signal.

The LMC662 is from the datasheet example of the ADC: https://www.ti.com/lit/ds/symlink/adc1175.pdf see page 18. Why is it an odd choice?

The extra low input bias current of the LMC662 is not required and it is not a low noise precision part.  But since the ADC resolution is only 8 bits, the LMC662 should be fine.  The LMC6082 is a higher precision LMC662 and would be better.

[FrankBuss]

Attached is a new version of the circuit diagram, and a Spice simulation. I added the compensation capacitors, are the values right? And I fixed the wrong transistor orientation, added some load resistors to VRT and VRB, just in case they are needed, and added an offset to the ADC driver OpAmp. First I tried to generate the offset with the LMC662, but it was not strong enough, so I use the LMH6702 for this as well. I found Spice models for it and could simulate it with LTSpice, at least in the simulation it looks good but it clips at about 3.5 V, I hope this is sufficient. But with the 2 new pots I can even adjust the gain and offset perfectly, so I don't need to do this in software.

But now I wonder if the ADA4622 can drive the low impedance input of LMH6702? There is a Spice model as well for this OpAmp, but don't know if it is worth the effort to simulate this, if someone can tell me if it works.

[Kleinstein]

I would prefer to have the trimmer cap towards ground. This makes it less sensitive to parasitic capacitance, e.g. when you trim it. Chances are the capacitance can be a little smaller.

AFAIK there is no need to have the same impedance on both inputs of a current feedback OP - they are different internally anyway. So the load to the ADA4622 can be lower.  The divider still looks reversed (e.g. more likely R12 and R18 swapped) So less amplitude is lost there. With only a small amplitude a load of some 400 Ohms could still be OK, though it does not help to have the resistance so low.

I have not looked up the DS for the LMH6702, but the FB impedance looks rather low - I don't think one would need the full bandwidth.

P.S. The 237 Ohms FB are OK for the LMH6702, but the LMH6702 is way to fast (some 700 MHz BW) here. No need for much faster then 50 MHz, especially with only 8 Bit. It would be more like using a normal voltage FB OP and add capacitance to additionally limit the BW.

[David Hess]

Kleinstein covered most of what I would have said.

If the trimmer capacitor is across R3, then it has to be larger which is inconvenient but the rotor can be on the ground side so the adjustment screwdriver has less or no effect while making the adjustment.

I agree about driving U2.  U4A might have trouble driving the low impedance of divider R12 and R18.  Ideally that divider is not needed at all.  What about decreasing the value of R3 for more input attenuation?  Note that if the impedance of divider R12 and R18 is increased too much, then it will require compensation also.

Adjustment RV1 should be on the input side instead of the feedback side.  The feedback resistance of a current feedback amplifier controls its performance and is usually fixed according to the datasheet specifications.

R10 should go to the positive supply.  Q1 has to source current into the positive ADC reference pin while Q2 has to sink current out of the negative ADC reference pin.  Just a resistor between VRT and VRB may be sufficient.

[FrankBuss]

Thanks, I will change it. The reason for the LMH6702 according to the datasheet of the ADC1175 is that it can drive dynamic capacitance at high speed. But I agree, for a few MHz analog bandwidth and 10 MHz sampling rate, maybe it is overkill. Which normal 50 MHz voltage OpAmp would you recommend, that can drive the dynamic capacitance of the ADC? The datasheet says, the ADC input jumps from 4 pF to 11 pF and back when changing the clock level.

Another question: the voltage supply for the ADC1175 has some strange arrangement with a ferrite bead, and they say the 5V supply has to be clean. But the voltage supply would be from 5V USB power from a PC, so I guess not very clean, which is the reason that I didn't even bother with the ferrite bead. But I don't mind if I get only like 5 or 6 bits effective resolution. Would this be possible? Or is there a way to make the 5V USB power a bit "cleaner"?

I think I will change the circuit to use individual modules for each input stage with input and ADC, connected with pin headers to a base board. Then I can build just one board first and the other boards when it works. And the individual modules could be used for other projects as well. Or I could even design a base board for 8 modules (I would need a fast 3-to-8 de-mux IC then, best with break-before-make outputs, to drive the many OE inputs), and only populate as many as I need.

[David Hess]

Thanks, I will change it. The reason for the LMH6702 according to the datasheet of the ADC1175 is that it can drive dynamic capacitance at high speed. But I agree, for a few MHz analog bandwidth and 10 MHz sampling rate, maybe it is overkill. Which normal 50 MHz voltage OpAmp would you recommend, that can drive the dynamic capacitance of the ADC? The datasheet says, the ADC input jumps from 4 pF to 11 pF and back when changing the clock level.

I did not check it but that is what I figured.  It is not surprising at all that the operational amplifier driving the ADC is so much faster than apparently necessary because it needs to drive the dynamic capacitance.  There are lots of suitable parts but if TI recommended the LMH6702 then it is a sure thing.

Another question: the voltage supply for the ADC1175 has some strange arrangement with a ferrite bead, and they say the 5V supply has to be clean. But the voltage supply would be from 5V USB power from a PC, so I guess not very clean, which is the reason that I didn't even bother with the ferrite bead. But I don't mind if I get only like 5 or 6 bits effective resolution. Would this be possible? Or is there a way to make the 5V USB power a bit "cleaner"?

An RLC decoupling network and then a ferrite bead and capacitor will help a lot.  But watch out for any ground loop formed between the USB ground and the signal grounds.

[FrankBuss]

Ok, next version. I separated the ADC module and the Arduino shield, and I added ferrite beads to the power supply for the ADC. Does this look right for the decoupling? The ADC datasheet recommended this ferrite bead, which has 780 ohm at 100 MHz. I hope this is the same in SMD.

I simulated the ADA4622 and looks like it can drive the low impedance, so I will keep the LMH6702 as in the example circuit from the ADC datasheet.

[splin]

I have a few issues ith your cct. First, the input stage needs rethinking. Problem is that you want a few MHz BW, but that 9Meg resistor along with say 3pF of input/stray capacitance of the opamp will act as an approx 6kHz LPF. Stray capacitance will also dramatically alter the divider ratio at high frequencies. Eg. if each resistor has only 1pF of parasitic parallel capacitance, the divider ratio is down from 10:1 to 5:1 by 37kHz.

If you don't want to reduce the input impedance by using much lower resistor values, then you have a few choices:

1) Use much lower value resistors in the divider, but this lowers the input impedance correspondingly.

2) Parallel each resistor in the divider with capacitors to swamp the parasitics, with values in the same ratio as the resistors (as seen in oscilloscope input ccts). One of the capacitors will need to be trimmable as they will drift with temperature and time relative to each other and the resistors. Alternatively, as your accuracy requirements are modest, you could probably use low tempco capacitors (NPO) and select-on-test one of the capacitors.

3) Buffer the input with an opamp or transistor(s) followed by a low impedance divider. This would require supply voltages greater than the +/- 10V input signal which would be a pain.

Apart from the input buffer I think you've considerably over complicated the design given you only need 5 or 6 bits of precision:

4) You don't need a seperate reference - the 5V supply voltage should be more than adequate - a percent or two change of reference voltage won't be a problem. The high and low reference buffers aren't required - connect the reference high, VRT to 5V and low, VRB to 0V. You want the highest possible reference voltage (Vdd) to a) maximize the signal to noise ratio (not too important in this case) and b) to minimize the reduction ratio of the input divider which now only has to be 4:1.

5) You don't need a -5V supply; level shift the +/-10V input to the 0 to 5V input range of the ADC. If you don't mind a lower input resistance, you can get rid of the input buffer and use the ADC driver to do the level shifting (and attenuation in an inverting configuration) - see attached. The 200k ohm input resistance gives 1.9MHz BW according to the simulation but this is going to be dominated by parasitic capacitances around the input divider and opamp +Ve input. The R3/C2 filter values aren't designed - just a guess.

The ADA4891 is a high speed driver which is a lot cheaper than the LMH6702 and will be (way) more than adequate for your requirements. Slower, cheaper amps (OPA358?) are likely to be suitable given that you are only sampling at 10MSPS (rather than 20MSPS as assumed in the datasheet) and only need 5 or 6 bits.

Input protection is another issue. Even though you know what you are doing it would be a shame to accidentally damage it for the sake of a few diodes/transils etc.

[FrankBuss]

Thanks, looks good with just the ADA4891. I added two protection diodes as well, couldn't find a way to use the diode symbol, but works with an auto generated symbol. Attached is a LTSpice simulation circuit diagram. And I added another opamp to create the shift voltage. But might be better to connect R7 to a LM4040 with 4.1 V and not +5V.

Instead of connecting VRT to 5V, and VRB to 0V, I would use the suggestion in the datasheet to connect it to VRTS and VRBS for self biasing. VRTS is 2.6 V typical and VRBS 0.6 V typical. I guess there is a reason that not 0 V is used as the default lower limit? The datasheet wasn't clear for me, but I guess the converter doesn't work as linear near VDD and GND? Noise wouldn't be a problem for my application, but would be nice if I didn't have to re-calibrate it, if VDD changes a bit. I could use pots in series to R7 and R5 to adjust the center and scale it to exactly +/-10V for full scale.

I think the input impedance of 150k is no problem for my application to sample the signals of a programmer. If I want to sample some sensitive analog circuits, I can always use an external pre-amplifier.

[FrankBuss]

New version is attached. It is getting really small.

[splin]

Thanks, looks good with just the ADA4891. I added two protection diodes as well, couldn't find a way to use the diode symbol, but works with an auto generated symbol. Attached is a LTSpice simulation circuit diagram. And I added another opamp to create the shift voltage. But might be better to connect R7 to a LM4040 with 4.1 V and not +5V.

Instead of connecting VRT to 5V, and VRB to 0V, I would use the suggestion in the datasheet to connect it to VRTS and VRBS for self biasing. VRTS is 2.6 V typical and VRBS 0.6 V typical. I guess there is a reason that not 0 V is used as the default lower limit? The datasheet wasn't clear for me, but I guess the converter doesn't work as linear near VDD and GND?

The suggested self-biasing scheme is probably provided for convenience when driving it with a non rail to rail amp. There is nothing in the datasheet to suggest that this is better than using Vdd, 0V for the reference - in fact it says:

The reference self-bias circuit of Figure 19 is very simple and performance is adequate for many applications. Superior performance can generally be achieved by driving the reference pins with a low impedance source.

You would be hard pressed to get lower impedance than Vdd and Vss. Of course, if Vdd is particularly noisy you might want to use a seperate reference - eg. a '3 cent regulator'. The ADC reference voltage needs to be matched to the input range to maximise the SNR. Since your input is greater than the maximum reference voltage (Vdd) you want the reference voltage to be as large as possible and the input attenuation to be as small as possible - ie.  5V reference with a divide by 4 attenuator.

Noise wouldn't be a problem for my application, but would be nice if I didn't have to re-calibrate it, if VDD changes a bit. I could use pots in series to R7 and R5 to adjust the center and scale it to exactly +/-10V for full scale.

Since you only need 5 or 6 bits of accuracy (or precision?) this seems unnecessary, but harmless.

I think the input impedance of 150k is no problem for my application to sample the signals of a programmer. If I want to sample some sensitive analog circuits, I can always use an external pre-amplifier.

What is the highest frequency you want to monitor? Even 150k is a bit high - LTSpice shows 1.9MHz, but any additional parasitics will reduce that - presumably LTSpice uses only the 4891 input capacitance in it's model.

You don't need to add a buffer amp for the offset voltage - given the 150k input resistance, a divider of 333/667 ohms to provide the 3.33V offset will barely impact the input attenuator at the cost of only 5mA from the 5V supply. If you aren't happy about that then consider using an inverting configuration as attached.

[EDIT] Note: C1 is to represent parasitic capacitance - change the value to see the impact on BW.

[FrankBuss]

Cool, only one OpAmp left now! Inverting is no problem. But with the positive reference I think VRTS will be better than the +5V, because it is USB powered, and can be very noisy and getting low like 4.8 V depending on cable quality etc., and would be nice if it would be at least maybe 0.2 V accurate. But I added some 0 ohm resistors, will try it on the prototype, if it works when VRB is connected to GND. And if VRTS is not good enough, I can bodge some voltage regulator at this input as well on the prototype. Attached is the next version.

I added an additional fuse at the input as well, costs only cents: https://www.digikey.de/short/j1th73 Just in case someone would try to measure mains with it, it would at least give a little bit protection. It is a fast fuse, I hope it doesn't blow from ESD? Should I use more than 250 mA?

[Kleinstein]

The positive input voltage would better be derived from the ADCs reference voltage, even if it takes another buffer.

A fuse at the input might be a good idea if the zerner protection is used. Otherwise it would nor help much - ESD would not blow even a 10 mA very fast fuse, unless dangerously high.

Depending on the resistor size, it might be a good idea to have the input resistor with 2 or 3 resistors in series to give it a higher withstanding voltage. Depending on the maximum frequency needed one might sill need small caps parallel to the resistors that set the gain. With only 150 K it is a lot lower impedance - so one might just get away without. With a 150 K resistor at the input (but without the zeners), this could be good enough to withstand mains voltage - at least if there are no mayor spikes. So I am not a big fan of the zeners at the input. I would more prefer something like a MOV and maybe a fusible resistor if really needed.

[splin]

But with the positive reference I think VRTS will be better than the +5V, because it is USB powered, and can be very noisy and getting low like 4.8 V depending on cable quality etc., and would be nice if it would be at least maybe 0.2 V accurate. But I added some 0 ohm resistors, will try it on the prototype, if it works when VRB is connected to GND. And if VRTS is not good enough, I can bodge some voltage regulator at this input as well on the prototype. Attached is the next version.

VRTS is just a resistor to Vdd so it will be just as noisy as Vdd. It would be a good idea to provide a reference even if it is a cheap regulator or a TL431 (< $.1) with a couple of resistors. That way you can get reasonable performance - it's never going to be a precision data aquisition module with only 8 bits - but it may be useful for other purposes. But do be careful to note this from the datasheet:

No pin should ever have a voltage on it that is in excess of the supply voltages or below ground, not even on a transient basis. This can be a problem upon application of power to a circuit. Be sure that the supplies to circuits  driving the CLK, OE, analog input and reference pins do not come up any faster than does the voltage at the ADC1175 power pins.

That shouldn't be a problem at power-on since 5V will be up first but at power down, depending on the amount of capacitance on the 5V rail compared to Vref, it's possible for Vref to hold up longer than Vdd - ie. don't put much capacitance on Vref in an attempt to make it as quiet as possible.

Also don't forget that the input bandwidth is ill-defined, depending on the capacitance across the feedback resistor. With 2pF, LTSpice shows the BW as 2.2MHz with the inverting configuration, but a few pF variance due to board layout, component parasitics etc will dramatically alter the BW. The capacitance wil be hard to measure directly so I guess you'll have to use a signal source and examine the ADC o/p to determine the actual BW.

[FrankBuss]

I don't think that I need a MOV or more protection, it is just for a little bit protection if I connect it to higher voltages, but not mains. But I changed the input resistor to 1206, should be good enough even for mains in combination with the fuse and the diode at the input. It is not a standard zener diode, but a TVS diode, this one, should be safe.

Attached is a new version of the schematic. I used this voltage regulator for the VRT input, optionally selectable with 0 ohm resistors. 4 V should give enough headroom with the low drop regulator, even for very low USB voltages. I also added some test points and cleaned up the circuit diagram, I think this might be the final version, at least for the first prototype and to measure something.

[FrankBuss]

No pin should ever have a voltage on it that is in excess of the supply voltages or below ground, not even on a transient basis. This can be a problem upon application of power to a circuit. Be sure that the supplies to circuits  driving the CLK, OE, analog input and reference pins do not come up any faster than does the voltage at the ADC1175 power pins.

That shouldn't be a problem at power-on since 5V will be up first but at power down, depending on the amount of capacitance on the 5V rail compared to Vref, it's possible for Vref to hold up longer than Vdd - ie. don't put much capacitance on Vref in an attempt to make it as quiet as possible.

The sample circuits on page 16 and 17 uses 10 uF capacitors for the reference inputs, and all powered from the same 5V supply. But I guess 1 uF might be sufficient and then no problem when powering down.

But I wonder why there is this warning in the datasheet. What worst can happen, if the voltage on VRT is higher from a small 10 uF capacitor for a short time? I guess all it would do is flowing into the VDD supply through the internal resistor, in case of the self-biasing cirucit, and if used disconnected from VRTS, then maybe flowing through some internal protection diodes to VDD. Shouldn't damage the chip.

[StillTrying]

On the last pdf the inverting and non-inverting inputs are reversed.

[Kleinstein]

......

The sample circuits on page 16 and 17 uses 10 uF capacitors for the reference inputs, and all powered from the same 5V supply. But I guess 1 uF might be sufficient and then no problem when powering down.

But I wonder why there is this warning in the datasheet. What worst can happen, if the voltage on VRT is higher from a small 10 uF capacitor for a short time? I guess all it would do is flowing into the VDD supply through the internal resistor, in case of the self-biasing cirucit, and if used disconnected from VRTS, then maybe flowing through some internal protection diodes to VDD. Shouldn't damage the chip.

The problem with a voltage higher than the supply, it that the protective diodes at the pins are actually kind of gates of parasitic thyristors. It only take enough current for a short time to trigger a latch up. It depends on the chip how much current is needed. That extra warning might be there because the chip might be a little sensitive.

The point that saves the day is that there are no other parts at the supply that can bring drown the 4/5 V supply fast. This kind of limits the current on the VDD side. The worst case would be some short, fast dropout at VDD (e.g. someone connecting an empty 1000 µF cap).

[FrankBuss]

Ok, attached is a new version of the ADC. I think it is not a good idea to make the ADC-in pin available at the pin header, and the OpAmp is corrected, and some additional pins for measuring the current consumption are added. I think now I can start with the layout.

And the Arduino shield form-factor base board is attached. I used this clock driver, because I decided to allow up to 8 ADC modules, and might be a bit too much load for the FPGA pin output for a clean clock signal.

To minimize the pin count for the output enable pin, I used this de-mux. I couldn't find any information about how it behaves when switching. Is it break-before-make? I guess it is not that important, because would be only a very short time, but a break-before-make behavior would be good to minimize spikes, if multiple ADC module data outputs are driving the bus at the same time.

[FrankBuss]

I don't think I can do the high sampling rate with just 8 data pins. Initially I planned to use the OE pin and query all 4 channels between samples. But the required setup and hold times and the strange 2.5 clock pipeline delay, would make this very critical for 4 channels, and impossible for 8 channels. I could add some high speed buffers, but I decided to use a DE10 Nano, which has enough GPIO pins to sample 8 channel all in parallel. This is the main board:

https://github.com/FrankBuss/adc4/blob/master/kicad/adc/adc.pdf

And this is one channel:

https://github.com/FrankBuss/adc4/blob/master/kicad/adc/adc1-ADC1.pdf

I also changed the ADC1175 to the ADC1175-50, which can sample with up to 50 MHz, and doesn't cost much more. I guess I would need to reduce C5 then for a higher analog bandwidth? But I think it is a good idea anyway, because with 10 MHz it would be more accurate.

[StillTrying]

"I guess I would need to reduce C5 then for a higher analog bandwidth?"

C5's 470p seems a very large value to me, giving the op amp's output a lot to do, I'd have thought only 22 - 47p would be enough, and less chance of the output overshooting.
I'd be tempted to put about 22 - 47n of decoupling on the op amps non-inverting input.

[FrankBuss]

Right, the decoupling capacitor is a good idea after the pot. I added the same 100 nF as already used, shouldn't make a difference. And I fixed the OpAmp power supply and changed the ADC-in capacitor to 47p. Will try it in the real hardware which value makes sense. 10 MHz analog bandwidth would be nice.