20 bit up/down counter, anything more elegant than a bunch of cascaded 4516's?

[Jester]

I need to build a 20 bit, binary up/down counter.

I don't need preload, but I do need all the bits, so 4040 etc. won't work.

I suppose I can cascade a bunch of 4516's, just messy with only 4 bits per chip. The 74...869 is 8 bit, but they are really expensive. There must be a better solution other than programming a small uC?

I feel like I'm missing something even after searching up/down counters with google.

[Kleinstein]

I don't know common up/down counters with more than 4 bits. There are difference version how up/down are combined.
The 4040 has all the outputs for 12 bits - however it is just a simple counter, no up/down.

As an alternative to a µC, there are also CPLDs, programmable logic chip that should be capable to do up/down counting for quite some bits.

[Benta]

I agree, the 4516 (or 74HC types) are probably the solution if you want to avoid CPLDs. At least they're cheap

[scuzzyTerminator]

A parametric search at digikey found these 8-bit devices pretty quick. Is TTL OK?

SN74AS867, SN74AS869: http://www.ti.com/lit/ds/symlink/sn74as867.pdf

[Benta]

A parametric search at digikey found these 8-bit devices pretty quick. Is TTL OK?

SN74AS867, SN74AS869: http://www.ti.com/lit/ds/symlink/sn74as867.pdf

Read the OP. He already found those...

[edavid]

I agree, the 4516 (or 74HC types) are probably the solution if you want to avoid CPLDs. At least they're cheap

74HC4516 isn't available.  I think 74HC193 is the best HC option.

[fchk]

A LCMXO256C-3TN100C is available for 2.58$ and has more than enough logic blocks for your task. It's TQFP100, so hand-solderable.

There are even cheaper ones, but these are BGA packages and difficult to solder at home.

[james_s]

XC9536 CPLD is $1.96 in single quantities and comes in a 44 pin TQFP package. As an added bonus it is available on inexpensive Chinese dev boards.

[xyrtek]

Is this elegant enough?

Hope you are proud I had to dig through old project boxes.

[max_torque]

How fast do you need to count?

[SiliconWizard]

There's the 74LS491 which is 10-bit, but available nowhere except brokers. Not cheap either. I've found some for about $5 each, but this is clearly not a viable solution if you need regular supply.
I've also found the SN74LV8154 which is interesting but doesn't seem to do down-counting, and the counter register(s) are available through some kind of MUX, so that may not be practical for your application if you need all 20 bits at once. Haven't found/or don't know of any other current and available IC for your requirements.

Is this going to be a product? If so, frankly, a small CPLD would likely be the cheapest and best long-term solution, and depending on the other logic parts in your design, may even allow you to significantly reduce the parts number. If you're uncomfortable programming one, I'm sure people here can give you source code for it (a few lines of code should do the trick) and programming tool's cost shouldn't be an issue at all. If it's going to be only a prototype (or a few of them), then I'm not sure I see the problem with parts that are around $5 or even $10 (yes very expensive for what they do, but the time you used for finding alternate solutions is probably worth a lot more ).

[kony]

XC9572XL. Few lines of verilog, almost fully remappable pinout, under a 1$/pc even in small qty and with space to spare for other glue logic still. Or any other flavour of CPLD.

[edavid]

XC9572XL. Few lines of verilog, almost fully remappable pinout, under a 1$/pc even in small qty and with space to spare for other glue logic still. Or any other flavour of CPLD.

For those who have experience with these CPLDs, how many macrocells does it take to implement an up/down counter stage?

[NiHaoMike]

XC9572XL. Few lines of verilog, almost fully remappable pinout, under a 1$/pc even in small qty and with space to spare for other glue logic still. Or any other flavour of CPLD.

For those who have experience with these CPLDs, how many macrocells does it take to implement an up/down counter stage?

Download the free version of ISE and try compiling a design yourself.

[kony]

Just did it for a hell of it - gated up/down counter with synchronnous reset is 20 marcocells (that is less than 30% of the resources of the XC9572XL).

[janoc]

XC9572XL. Few lines of verilog, almost fully remappable pinout, under a 1$/pc even in small qty and with space to spare for other glue logic still. Or any other flavour of CPLD.

For those who have experience with these CPLDs, how many macrocells does it take to implement an up/down counter stage?

One cell of these is one flip-flop + some logic, so one bit of the counter ~ 1 cell. 9572 has 72 cells, there is also 9536 with 36 cells only (slightly cheaper but may not fit a 20 bit counter).