1.5 to 3 MHz frequency doubler circuit

[Wolfgang]

If you need to phase align with the original signal you can use a phase shifter before digitizing.
Another idea is a PLL, which does the same with more jitter.

[Buriedcode]

According to the datasheet, the amplifier can use its internal oscillator, which I assume is phase locked to the SCLK input:

The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the
internal clock (DCLK) running at 512 times the PWM switching frequency.

With an SCLK of 1.536MHz you either have a sample rate of 24kHz with 64 SCLK periods per frame, or more likely 48kHz with only 32 sclk's per frame.  It seems the amplifier can accept this, so I'm not sure you really need a frequency doubler.  It *should* have its own internal 24.576MHz clock running from a PLL.

The amplifier looks quite impressive, I might pick one up to play with - has a number of advanced features!

[dmendesf]

Look for 74hct9046. It's a newer version of 4046 with a few bugs ironed out. I've used it to generate > 15MHz signals, although the design equations don't work very well at this frequency and some trial and error is mandatory.

[edavid]

Look for 74hct9046. It's a newer version of 4046 with a few bugs ironed out. I've used it to generate > 15MHz signals, although the design equations don't work very well at this frequency and some trial and error is mandatory.

OP is running his circuit at 3.3V, so the 74HCT9046 would not work.  (Also, the improvements don't matter for his application.)

[langwadt]

According to the datasheet, the amplifier can use its internal oscillator, which I assume is phase locked to the SCLK input:

The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the
internal clock (DCLK) running at 512 times the PWM switching frequency.

With an SCLK of 1.536MHz you either have a sample rate of 24kHz with 64 SCLK periods per frame, or more likely 48kHz with only 32 sclk's per frame.  It seems the amplifier can accept this, so I'm not sure you really need a frequency doubler.  It *should* have its own internal 24.576MHz clock running from a PLL.

I looked at the datasheet and is clear as mud on how the it should be clocked, but afaict it will mute the output if it isn't clocked
just right

[Gandalf_Sr]

I looked at the datasheet and is clear as mud on how the it should be clocked, but afaict it will mute the output if it isn't clocked
just right

I have to disagree, I think mud is way clearer than the datasheet.  In my case the Amp was giving me no sound and no error indications (by reading the I2C error register).  After a month, TI eventually gave help on their e2e forum (after I'd reached out via my contacts in TI) but that was when it was revealed that what I needed was a MCLK at double the SCLK.  Seriously TI, from a designer seeking help perspective, you may as well have moved to another planet - maybe you did?

To save me some time (I'm on a cruise ship about 100 miles NE from Cape Horn and internet is a bit slow here), can anyone point me to a schematic for the 74HC4046A used with an external divider that will run at 3.3V?

[Benta]

To save me some time (I'm on a cruise ship about 100 miles NE from Cape Horn and internet is a bit slow here), can anyone point me to a schematic for the 74HC4046A used with an external divider that will run at 3.3V?

Here you go (written by a friend of mine):

[Gandalf_Sr]

Wow, thanks

Now 'all' I have to do is remember how to do Laplace transforms.

[Benta]

Wow, thanks

Now 'all' I have to do is remember how to do Laplace transforms.

Not necessary, already done for you. Use the "practical example" section.
However, you have a different task: with the relatively high frequency from the PFD, you'll need to find an opamp that:
- has at least 25 MHz GBW
- has rail-to-rail inputs and outputs
- is unity-gain stable
- will operate at 3.3 V

[edavid]

Not necessary, already done for you. Use the "practical example" section.
However, you have a different task: with the relatively high frequency from the PFD, you'll need to find an opamp that:
- has at least 25 MHz GBW
- has rail-to-rail inputs and outputs
- is unity-gain stable
- will operate at 3.3 V

For 2X multiplication of a constant frequency clock, you don't need (or want) a Type 2 loop.  The XOR phase detector and a simple passive filter will work fine.

[Gandalf_Sr]

The cost difference between an Op Amp and a D-Type flip flop is unimportant but the flip flop (say a 74HC174) has a 13 nS delay which is significant given the periodic time for the 3.072 MHz output is 325.5 nS. Maybe the Op Amp is the way to go? Or can I realize the divide by 2 using a faster logic family? Remember that my supply voltage is 3.3V.

[Cruise update] Docked in Ushuaia with perfect weather - we went around Cape Horn yesterday in near millpond like conditions.

[edavid]

The cost difference between an Op Amp and a D-Type flip flop is unimportant but the flip flop (say a 74HC174) has a 13 nS delay which is significant given the periodic time for the 3.072 MHz output is 325.5 nS. Maybe the Op Amp is the way to go? Or can I realize the divide by 2 using a faster logic family? Remember that my supply voltage is 3.3V.

You are mixing up 2 different red herrings:

1. The op amp would be part of a PLL active loop filter, which you wouldn't need.

2. The divider flip flop (74HC74, not 174) propagation delay would be removed by the action of the PLL.  The offset between the two clocks is determined by the phase detector characteristics.

[Benta]

I have to agree with edavid.
The flipflop or divider delay in the PLL would rather advance the output of the VCO, so the VCO output will lead the input. This can easily be compensated, but still...

The RC delay plus XOR is still the best solution for a simple constant frequency doubling IMO.

[Gandalf_Sr]

...The divider flip flop (74HC74, not 174) propagation delay would be removed by the action of the PLL.  The offset between the two clocks is determined by the phase detector characteristics.

If the phase comparator compares the original 1.536 MHz clock input to the VCO output fed through a /2 flip fop that introduces a 13 nS delay then surely the output signal edges will lead the edges of the input signal by 13 nS?

I agree that the XOR should work but it doesn't, at least not reliably.  I have a thread running on this on TI's e2e forum - the question is why the TAS5755M doesn't like my slightly jittery and variable M/S ratio doubled MCLK, maybe they'll shed some light on this eventually?  Perhaps the fact that the SCLK and associated signals come on before the MCLK does is something the Amp doesn't like?

Thanks for the proactive input folks, and a Happy New Year to you all.

[spec]

Just a suggestion, but wouln't the SN74LV4046A PLL chip be worth considering. It is high performance and 3V3 compatible.

http://www.ti.com/lit/ds/symlink/sn74lv4046a.pdf

[spec]

(3MHz = 3.072 MHz and 1.5MHz = 1.536 MHz throughout)

This is an intriguing thread, because the requirement is a lot more demanding than would first appear.

The suggested solutions so far (hope I have this right) are:

• XOR with open loop mark to space ratio (MSR) definition
• PLL
• Transformer

I have been looking at other approaches as well:

• logic frequency doubling (similar to XOR above) with two analog servo control loops to provide an accurate 1:1 mark to space ratio of the 3MHz signal (LDAS)
• Digital Sampling Counter (DSC)

The LDAS approach is reasonably self explanatory, so I will only describe the DSC approach:

The inputs to the DSC are the 1.5 MHz reference signal, and a clock reference signal (CRS) of as high a frequency as the logic in use will take, say 100mHz, for the SN74LVxA family of logic chips running at a 3V3 supply line. The CRS absolute frequency is unimportant. The only requirement is that it is frequency stable for around 10uS and jitter free.

A synchronous digital counter (DC1), clocked by CRS, counts the number of CRS periods in one cycle of the 1.5Mhz signal and loads 1/4 of the digital value into another synchronous digital counter (DC2) which is also clocked by CRS.

The output of DC2 would then be a 3MHz signal with a 1:1 MSR, synced to the 1.5MHz  reference signal.

The only drift would be due to any drift of CRS over a 10uS period.

Of course, if you really wanted to do a Rolls Royce job you could use ECL or PECL to get the sampling rate right up.

The design of the DSC would be pretty straight forward for a digital designer and the physical the same. I recon the DSC could be implemented with four chips and possibly a 100mHz Xtal oscillator, but I haven't done a trial schematic.

This is really thinking aloud but I would be interested to hear the general view of these two approaches, especially the DSC approach.

[edavid]

I agree that the XOR should work but it doesn't, at least not reliably.  I have a thread running on this on TI's e2e forum - the question is why the TAS5755M doesn't like my slightly jittery and variable M/S ratio doubled MCLK, maybe they'll shed some light on this eventually?  Perhaps the fact that the SCLK and associated signals come on before the MCLK does is something the Amp doesn't like?

We are talking about using an XOR phase detector for a PLL doubler, *not* about an XOR frequency doubler.

[edavid]

This is really thinking aloud but I would be interested to hear the general view of these two approaches, especially the DSC approach.

This is more commonly called a Frequency Locked Loop.  It has its applications, but for a fixed frequency multiplier it has more jitter than the simpler open loop or PLL approaches, so it's not a good idea.

[spec]

This is really thinking aloud but I would be interested to hear the general view of these two approaches, especially the DSC approach.

This is more commonly called a Frequency Locked Loop.  It has its applications, but for a fixed frequency multiplier it has more jitter than the simpler open loop or PLL approaches, so it's not a good idea.

Yes, I was wondering about the jitter. Thanks for the info

[Benta]

I agree that the XOR should work but it doesn't, at least not reliably.  I have a thread running on this on TI's e2e forum - the question is why the TAS5755M doesn't like my slightly jittery and variable M/S ratio doubled MCLK, maybe they'll shed some light on this eventually?  Perhaps the fact that the SCLK and associated signals come on before the MCLK does is something the Amp doesn't like?

We are talking about using an XOR phase detector for a PLL doubler, *not* about an XOR frequency doubler.

Problem is, that the simple XOR phase/frequency detector does not have phase coherence. It can be anywhere between -90 and +90 degrees.

[edavid]

Problem is, that the simple XOR phase/frequency detector does not have phase coherence. It can be anywhere between -90 and +90 degrees.

That is not correct.  A PLL with filtered XOR phase detector will always lock at 90 degrees phase difference. 

[Benta]

Problem is, that the simple XOR phase/frequency detector does not have phase coherence. It can be anywhere between -90 and +90 degrees.

That is not correct.  A PLL with filtered XOR phase detector will always lock at 90 degrees phase difference.

Your understanding is incorrect. A type 1 PLL (which an XOR PD is) has varying phase difference between the input signals, depending on which voltage the VCO needs. Otherwise it would not work as FM detector, for instance. I recommend that you invest in a Gardner ~100$).

[nick_d]

Check specs on TAS5755M master clock, it is highly unlikely it would need a 50% duty cycle unless it's sampling the data on both clock edges. At around 10MHz with HC logic the 50% duty cycle becomes inportant to avoid pulses that are too narrow for the logic to handle, but this is unlikely to be a problem at 3MHz and at 3.3V you will be using more advanced logic anyway. So how I would handle this is the Schmitt XOR... you only need 1 gate, just put the undelayed 1.5MHz in one input and the RC delayed 1.5MHz in the other. The Schmitt wouldn't be needed with HC logic at MHz rates since by the time it had switched the input would be well past threshold preventing oscillation, but it might be beneficial with more advanced logic. If you are usng 1 gate packages get the Schmitt XOR. Otherwise if you have spare gates let us know and we may be able to see a way.
cheers, Nick

[Gandalf_Sr]

I ordered some parts from Digikey today so that I can try some of the approaches suggested here.
Quantity   Part Number   Manufacturer Part Number   Description   
10   296-17660-1-ND   SN74AUP1G79DCKR   IC FF D-TYPE SNGL 1BIT
2   296-14856-1-ND   SN74HC590ADWR   IC 8BIT BINARY COUNTR 3ST
10   296-27397-1-ND   SN74AUP1T86DCKR   IC GATE XOR SCHMITT 1CH
10   296-21048-1-ND   SN74LV4046ADGVR   IC LOGIC PLL W/VCO
10   712-1274-1-ND           500R07S220GV4T   CAP CER 22PF 50V C0G/NP0
10   TC33X-103ECT-ND   TC33X-2-103E         TRIMMER 10K OHM 0.1W J LEAD

Not much money and they will all come in for experimentation - the Caps are 2% vs the 20% ones that I used before