1.5 to 3 MHz frequency doubler circuit

[Gandalf_Sr]

I have a design where a Cypress BLE module feeds I2S audio data to a TAS5755M TI Amplifier.  The problem is that the Amp needs an extra clock signal called MCLK of 3.072 MHz and it needs to be a doubled, synched multiple the I2S SCLK signal of 1.536 MHz.  I built a circuit like this...

https://www.maximintegrated.com/en/app-notes/index.mvp/id/3327

But there's a lot of jitter and variations on the mark-space ratio on the output so it's very unreliable and only works occasionally.

I thought it would be simple to build a PLL circuit set up as a doubler with 1.536MHz in and 3.072 MHz out but all the ICs I've looked at have a minimum output frequency that's too low (I looked at the 74HC4046a and the PT7C4511).

Can anyone here suggest an IC or circuit that will meet my needs?  My operating voltage is 3.3V.

Thanks in advance.

[jpb]

I'm not a great expert but I thought the 4046 was happy producing kHz. The example in "The Art of Electronics" is using it go go from 60Hz to 61.44 kHz. So I'm surprised it can't do 3.072 MHz as being "too low".

[Gandalf_Sr]

Thanks for the suggestion.

Maybe there's a 4046 family member that will work but the CD4046B won't run properly at 3.3V and the max Fout is <3 MHz.  The 74HC4046A has a min VCO Fcenter of 12MHz - this is all from memory over my recent research so I may have made mistakes.  I'm at sea on a cruise in the S Atlantic and the Internet is a bit slow.

[soldar]

But there's a lot of jitter and variations on the mark-space ratio on the output so it's very unreliable and only works occasionally.

That circuit should work. Is the power supply to the comparator absolutely stable and filtered? If the input is a nicely cut rectangular signal then jitter should not be an issue and the circuit, should not have much jitter.

The duty cycle issue is different. The easiest way to have a 50% duty cycle is to start with double the frequency and then divide by two. 

[Gandalf_Sr]

I stuck with having to double as I can't get to the 3.072 MHz signal that presumably exists inside the Cypress BLE module (I asked).  I just posted in TI's e2e forum although it only went through on my 4th try - I have problems with that forum even when I'm on a light-speed connection, doing it over the ship's zoom satellite connection is almost impossible.

[SiliconWizard]

This simple circuit doubler has the benefit of getting you a synchronized clock. But the duty cycle of the output clock entirely depends on the delay block formed by R1/C1 and the comparator.
Have you adjusted R1 and C1 accordingly?

[Benta]

The comparator is unnecessary and just helps Maxim sell a device. An RC delay into a Schmitt trigger and then into the XOR is enough. You'll need to play around with the RC values.

[MasterT]

Dispute with what maxim-IC is recommend, I'd use differentiator   RC circuits

http://www.circuit-finder.com/categories/digital/377/frequency-doubler-with-4011

[edavid]

The 74HC4046A has a min VCO Fcenter of 12MHz - this is all from memory over my recent research so I may have made mistakes.

The datasheet headline reads:

Operating Frequency Range
-  Up to 18MHz (Typ) at VCC = 5V
-  Minimum Center Frequency of 12MHz at VCC = 4.5V

That means they guarantee it will go that high, not that it can't go lower.  There is no minimum VCO frequency.

That said, if you have access to toroid cores, you could build a simple full wave doubler circuit out of a transformer and a couple of diodes.  They work much better than XOR gate doublers.

[Benta]

Dispute with what maxim-IC is recommend, I'd use differentiator   RC circuits

http://www.circuit-finder.com/categories/digital/377/frequency-doubler-with-4011

That circuit won't give you control over the output duty cycle, but rather deliver spikes at double frequency.

[SiliconWizard]

The comparator is unnecessary and just helps Maxim sell a device. An RC delay into a Schmitt trigger and then into the XOR is enough. You'll need to play around with the RC values.

True. Note that if you use a 74AUP1G86 (single gate XOR), it has schmitt trigger inputs, so no additional component is necessary.

Of course an RC delay is not that stable, especially temperature-wise, so you'll inevitably get some drift of the duty cycle, but that should be ok for the op's application.

[ogden]

I have a design where a Cypress BLE module feeds I2S audio data to a TAS5755M TI Amplifier.  The problem is that the Amp needs an extra clock signal called MCLK of 3.072 MHz and it needs to be a doubled, synched multiple the I2S SCLK signal of 1.536 MHz.  I built a circuit like this...

You need tuned LC tank multiplier like http://electriciantraining.tpub.com/14181/css/Frequency-Multiplication-95.htm, fast comparator and divide by two flip-flop to generate 1x clock back from multiplied one

[Gandalf_Sr]

Wow, great responses guys, thanks

I have played with the R1 C1 values but, as has been predicted, the results can drift or be inconsistent.

Now I have several choices to look at:
1. Use a 74AUP1G86 XOR logic IC with Schmitt trigger inputs
1. Use a 74HC4046A PLL IC which will need a divide by 2 circuit for the feedback loop, probably just a JK flip flop
2. Use a tuned LC tank multiplier but won't that produce a sine wave output?

I'm discarding the transformer rectifier option as too expensive and large.

I will order components for all 3 and test each one.

Thanks again.

[ogden]

2. Use a tuned LC tank multiplier but won't that produce a sine wave output?

Yes. That's why comparator was mentioned - to convert sine to square wave.

[Gandalf_Sr]

2. Use a tuned LC tank multiplier but won't that produce a sine wave output?

Yes. That's why comparator was mentioned - to convert sine to square wave.

Sorry, not fully awake yet 

[Wolfgang]

I have a design where a Cypress BLE module feeds I2S audio data to a TAS5755M TI Amplifier.  The problem is that the Amp needs an extra clock signal called MCLK of 3.072 MHz and it needs to be a doubled, synched multiple the I2S SCLK signal of 1.536 MHz.  I built a circuit like this...

https://www.maximintegrated.com/en/app-notes/index.mvp/id/3327

But there's a lot of jitter and variations on the mark-space ratio on the output so it's very unreliable and only works occasionally.

I thought it would be simple to build a PLL circuit set up as a doubler with 1.536MHz in and 3.072 MHz out but all the ICs I've looked at have a minimum output frequency that's too low (I looked at the 74HC4046a and the PT7C4511).

Can anyone here suggest an IC or circuit that will meet my needs?  My operating voltage is 3.3V.

Thanks in advance.

The jitter free solution is a balanced doubler, like here (you need to scroll down a bit):

https://electronicprojectsforfun.wordpress.com/a-clean-23cm-signal-source/

The advantage of a balanced doubler is best signal quality with very low jitter and cancellation of harmonics.
You need to adapt the circuit to 3.3V. If you need a digital output, a Schmitt trigger could be added at the output.

[ogden]

The jitter free solution is a balanced doubler, like here (you need to scroll down a bit):

https://wordpress.com/view/electronicprojectsforfun.wordpress.com

The advantage of a balanced doubler is best signal quality with very low jitter and cancellation of harmonics.
You need to adapt the circuit to 3.3V. If you need a digital output, a Schmitt trigger could be added at the output.

URL does not look right.

[Wolfgang]

Thanks, I fixed it.

[edavid]

I'm discarding the transformer rectifier option as too expensive and large.

A T37-2 core, a few inches of wire, and a couple of diodes are expensive and large? 

[SiliconWizard]

I have played with the R1 C1 values but, as has been predicted, the results can drift or be inconsistent.

To get a much more precise and stable delay, you could also use a digital delay line instead of this RC circuit. Then the XOR gate doesn't need schmitt trigger inputs either.
Examples are DS1100L or DS1110L.
https://www.maximintegrated.com/en/products/digital/clock-generation-distribution/DS1100L.html
Not quite cheap but for a few bucks more (around $5 in small quantities), this will be a whole lot better.

[MasterT]

Dispute with what maxim-IC is recommend, I'd use differentiator   RC circuits

http://www.circuit-finder.com/categories/digital/377/frequency-doubler-with-4011

That circuit won't give you control over the output duty cycle, but rather deliver spikes at double frequency.

Have you checked a link? There is time/pulse diagrams, duty circle is manageable over R1C1 & R2C2 adjustment. 

[ogden]

The jitter free solution is a balanced doubler, like here (you need to scroll down a bit):

https://electronicprojectsforfun.wordpress.com/a-clean-23cm-signal-source/

OMFG! Everything about your universal signal source device is so... sexy. Many shall learn from you. I admire your attention to tiniest details down to "no improvements left" point.

[Gandalf_Sr]

Thanks for the further input guys.  The balanced doubler looks beautiful but it (seems) uses 2 transformers.  Part of the original requirement is that the doubled frequency is aligned with the input frequency; won't the transformers add phase shifts as the signal passes through them?

Also, the roll-your-own approach is problematic, I'd much rather build with off-the-shelf components.

If I can make the PLL device work down to 3.072 MHz it should be fine if I add a comparator or Schmitt trigger on the output but it seems like overkill - I wonder why the TAS5755M is so fussy about the I2S input signal; maybe it needs a register change to affect the way it responds to a bad clock input that becomes OK?

[S. American Cruise Update] At sea today, going round Cape Horn tomorrow, and Ushuaia the day after that - been lucky with great weather so far. Wildlife is amazing: penguins, flamingoes, parrots, owls, and sea lions to name but a few.  Will get close to 60 degrees South at some point.

[Wolfgang]

Hi,

if you insist on stock components you can use Mini Circuits transformers instead of the Balun cores. The rest are stock inductors and capacitors.
To phase align the doubled frequency to the fundamental, just divide the digital output by two (74HC74).

[Gandalf_Sr]

The need for the doubled frequency comes because the TAS5755M amplifier needs an I2S master clock (MCLK) signal that is not provided by the normal I2S signal lineup which provides a serial clock (SCLK), serial data (SDAT), and L/R or word clock (WCLK).  So there's data that's aligned with the SCLK clock and my requirement is for a MCLK clock that's double the SCLK but also phase aligned with it, I am pretty sure that I can't use a generated SCLK to feed into the BT module to make it use that clock for generating the I2S signals.  Although it's a powerful Amp, the TAS5755M has proved annoying in this respect; the previous design used the same BT module with an Analog Devices SSM3582 Amp that's less powerful but which doesn't need the MCLK clock - the decision to move to the TAS5755M Amp was to get more power output but the MCLK signal and overcoming all its quirks has been a pain in the posterior.