(Yet Another) DIY Multislope ADC

[NNNI]

I just did some INL runs, and the results are pretty interesting. I think the sawtooth like shape means that I got the calibration constants for the residue ADC wrong.

My calibration scheme is as follows: Disconnect input from the integrator, turn on +ref for 1/16 of a runup cycle, measure residue difference to obtain a 'runup-down' (RUD) value, then turn on -ref for 1/16 of a runup cycle, measure difference to obtain a 'runup-up' (RUU) value, and use them in the formula I posted above.

Update: there was an error in the runup math, INL after the fix is also posted.

[Kleinstein]

Even with the fix the INL curve still looks not that great. The General parabola shape with the U² part is expected from the R_on modulation due to the rather high input current. The more local variations are what looks strange and not so good.

The scale factor calibration with only a short pulse may not be very accurate. It includes the effect of 2 switching events that can add a bit extra charge injection. Ideally the pattern to test would be more like  2+x µs positive and 2-x µs of negative. With x of some 0.2 to 0.5.  So the same pulse squence, just a little different pulse length. One would likely also need a few repeats and a way to make sure to stay inside the valid range: e.g. decide on which type of pulse to use depending on the charge to start with.

There may also be a problem with the INL test or noise (e.g. ref. noise or drift). There is quite some difference between the different runs.

[iMo]

..The project files are available, so it should be possible to get your own set of boards for experimentation, or replicate the core circuit (it's quite simple) on a breadboard..

Yep, the analog part of the design is an another story which we have not elaborated yet
My basic motivation has been to have a look at the 2040/PIO and its applicability. Of course it could be done by a stm32xxx (here we lack the PIO) or an fpga+MCU (here the complexity is higher) as well.
Hopefully rPi company will come with the rp2041 soon - with the fixed ADC, and with 4xPIO with 256 instructions each

 
The new 2350 with 9.2b ENOB ADC and still only 32 instructions per PIO (with 4 SMs)..
They enhanced the PIO's number (3 now) and PIOs functionality, however.
Btw., I've searched through the 2350 datasheet, searching for "32 instructions" and "64 instructions" and found only a single info in the Fig.43..

[diminddl]

still only 32 instructions per PIO (with 4 SMs)..

I believe the PIO architecture has a fixed 5 bit (32 value) program counter, all instructions expect this and I would imagine that re designing it from scratch didn't make much sense. PIO did get some other more subtle improvements that are nice. Also, since the new PIO IRQs can communicate between blocks you can pretty trivially harvest all the instructions in other blocks. Using the inter state machine IRQ flags you are looking at 96 instructions with a bit of overhead.