[PCB Layout] My first "High Speed" PCB

[jack burton]

Hi all,
I used Cadence for almost 6 years then my company switched to Altium Designer 18 and gave me time and budget to learn and build my first High Speed Design, that means lenght-matched and differential paired signals.
In the past we used to work mainly with Cortex M4 MCU from STM, so High Speed PCBs were not our priority... but now we're starting  to use Cortex M7 and try to realize more integrated boards, with SRAM and other chips connected via 32bit bus.
I'm trying to use schematics of ST demo boards as reference designs..
I've never done a tuned bus, so i started placing MCU and other components involved in the 32bit bus: a SRAM and a connector for another board, plus a nand flash.
I used T-branch topology, and my first impression is that i'm extremely slow....
Before it's too late i wanna share my design so far to ask you your impressions and your suggestion...
When i started the design i had in mind the goal to keep the bus as compact as possible.. but i think i miss some skill to achieve it..



As you can see i have the MCU on the top, memory on the left side and connectors on the right ..
At this point i have a doubt: should i try to restrict the tracks of the bus or should i start to tune them ?
I feel like every step i can take now it's wrong..

Any suggestion would be appreciated
Thank you in advance for your help.
Bye

[ovnr]

Define "high speed". A T-branched topology like this is probably not what you want for actual high-speed signals, for one, due to reflections. And it doesn't really seem length-matched either?

Also, I'd recommend using resistor packs instead of the massive pile of discrete resistors near the MCU.

[Ice-Tea]

Just some high level considerations...

- Whatever problems you might run into signal integrity wise: it will be less if you keep your distances short. You should be able to keep it all a lot shorter, more compact.
- Do you need parallel flash? Your first question should always be: what can I throw of this board. Would a SPI-flash do? How much SRAM do you need? Do you really need a 32 bit bus?

[jack burton]

Thank you for the quick reply,

Define "high speed". A T-branched topology like this is probably not what you want for actual high-speed signals, for one, due to reflections. And it doesn't really seem length-matched either?

Also, I'd recommend using resistor packs instead of the massive pile of discrete resistors near the MCU.

I just finished to connect bus nets and i wanna ask your opinion before proceeding.
I know that T-branch could be not the right topology, but the board i'm trying to design should mount another board on the bus interface.
The board connected on the 32bit bus is a AXM88180-EVB-RTL8211E-1 SMDK2440 Demo Board, that is a demo board of a  Gigabit transceiver chip from Asix:


§As you can see this board has not lenght-matched tracks, so i though to tune only the left side of the branch, toward memory chip.
Another option could be to use fly-by topology, going to connector with not-matched tracks, and then start from the connector with lenght matched tracks toward the memory chip (of course lenght-matched over the whole tracks, not only starting from connector).

Just some high level considerations...

- Whatever problems you might run into signal integrity wise: it will be less if you keep your distances short. You should be able to keep it all a lot shorter, more compact.
- Do you need parallel flash? Your first question should always be: what can I throw of this board. Would a SPI-flash do? How much SRAM do you need? Do you really need a 32 bit bus?

We need 32-bit bus and external memory because we are going to port graphics and web apps from other M4 boards on this new one.

These are all the mandatory stuffs i have to place on the bus :
 



Any suggestions would be appreciated.
thank you.

[TiN]

Ouch First you'd want to get rid of those 2.54mm spacing pin array connectors. High speed connectors usually have 50 ohm matched impedance, and SMT. You will get lots of reflection and SI issues with huge thru-hole connectors on the bus like this. I mean it will probably work on 100 Megs or so, but that's big no-no in proper high-speed PCB on the bus. Usually best results are if you have point-point routing for stuff like memory I/O. If you really need connector on the bus - place it between your MCU and SRAM chip, so signal routing flow "thru" connector and ends up on SRAM chip.

For board-board high-speed connectors you'd want something like Samtec or Mictor connectors. Also use multi-layer design, all signals should be impedance matched and properly referenced (to ground or VCC, depends on topology in your design and datasheet requirements for your SRAM/CPU). Such board would be much better on 4-layer, with signal routing on top + bottom, while your GND will go solid on inner layer 1 (under TOP) and VCC on remaining layer. Keeping impedance intact is usually more important for high-speed than small mismatches in flight time on the bus, as those are often compensated out by memory controller I/O logic during training.

[jack burton]

Ouch First you'd want to get rid of those 2.54mm spacing pin array connectors. High speed connectors usually have 50 ohm matched impedance, and SMT. You will get lots of reflection and SI issues with huge thru-hole connectors on the bus like this. I mean it will probably work on 100 Megs or so, but that's big no-no in proper high-speed PCB on the bus. Usually best results are if you have point-point routing for stuff like memory I/O. If you really need connector on the bus - place it between your MCU and SRAM chip, so signal routing flow "thru" connector and ends up on SRAM chip.

For board-board high-speed connectors you'd want something like Samtec or Mictor connectors. Also use multi-layer design, all signals should be impedance matched and properly referenced (to ground or VCC, depends on topology in your design and datasheet requirements for your SRAM/CPU). Such board would be much better on 4-layer, with signal routing on top + bottom, while your GND will go solid on inner layer 1 (under TOP) and VCC on remaining layer. Keeping impedance intact is usually more important for high-speed than small mismatches in flight time on the bus, as those are often compensated out by memory controller I/O logic during training.

Hi TiN,
unfortunately i can't use connectors with different pin-to-pin spacing because the board that I have to connect to is already defined in connectors and pinout.
And if i used smd connectors probably i'd have no chance to place it so close, and however i'd need a looooots of vias to connect it to the bus, as i told , the pinout it's already defined (its the pinout of the demo board) and i can't swap pins.

I'm using a six layer PCB and of course i will use GND and VCC planes.
Contrary to what you said about the need of impedance control, i had read somewhere that in memory bus like this it's important to have lenght-matched tracks, while in differential paired bus like ddr or lvds impedance matching is important like lenght matching.

Anyway, i agree with the fact that probably fly-by topology as you suggested would be better in my case.

thank you.

[ovnr]

On a different topic: Is there a reason you're using an evaluation board as part of this entire thing?

In general I'd have thought it would be better to find a more modern SoC with built-in gigabit ethernet. You're already using BGAs and 6-layer boards; it's not like that's the hurdle.

[free_electron]

T-routing is not done. period. too many reflections.

Length tuning ... is , in a lot of cases, not critical.  What is the timing budget from data stable to clock edge ?
That you need to know first. Then you can figure out how much skew you can afford.

Even though this thing sounds 'impressive'. 'gigabit' et al... it is not hard to do 1 gigabit. run it over a 32 bit wide Data bus and you barely clock at 30MHz ... hardly needs tuning.... with some careful layout ( clock line longer than longest dataline by 1.5 times ) and a nice plane and some series termination ( if the host or transceiver doesn't have that on board. Most modern silicon has programmable drive strength so you can tune that using software ) and you are 99% there.

[jack burton]

Hi Ovnr,
in the final design i'm going to place the gigabit chip directly on my pcb, but now i'm using the Asix demo board mainly because we will use the pins on connectors also like test points and i'll spend less time on the layout.
The pcb i'm designing is intended as "training board", having connector maybe it's also a challenge to try to learn something more unusual..
I know there are other newers gigabit Soc, but i have to use M7 and this gigabit TRX in order to re-use drivers and stock chips we already have.

Thanks for the reply.

[jack burton]

T-routing is not done. period. too many reflections.

Length tuning ... is , in a lot of cases, not critical.  What is the timing budget from data stable to clock edge ?
That you need to know first. Then you can figure out how much skew you can afford.

Even though this thing sounds 'impressive'. 'gigabit' et al... it is not hard to do 1 gigabit. run it over a 32 bit wide Data bus and you barely clock at 30MHz ... hardly needs tuning.... with some careful layout ( clock line longer than longest dataline by 1.5 times ) and a nice plane and some series termination ( if the host or transceiver doesn't have that on board. Most modern silicon has programmable drive strength so you can tune that using software ) and you are 99% there.

Hi free_electron,
thanks for the reply.
I know that probably in this case lenght tuning is not critical, but i'm trying to gain some skill to get closer to real high speed design, so i started from this design.
Regarding the time budget... which the best way to calculate it ?
i'm using a 256 Mb Sdram from ISSI, (pn S42S32800J) with a STM32F7,
when i was looking for a formula or a method to estimate a lenght tolerance based on timing values, i was able to find only "common values" used by pcb designer..
Now in my pcb rules i have a tolerance of 0.635mm between Data tracks and the same valuse between address and control tracks.

[ovnr]

Well, for one: SDRAM isn't SRAM. Someone put a D in there, which screws up all the works.

In all seriousness: This is a 166 MHz part, and I assume you're going to be using it at 100+ MHz at least. Is that going to be fine for the AX88180 ethernet IC? Is it even going to work, connected to the STM32F7 with a memory controller configured for SDRAM?

[free_electron]

Well, for one: SDRAM isn't SRAM. Someone put a D in there, which screws up all the works.

In all seriousness: This is a 166 MHz part, and I assume you're going to be using it at 100+ MHz at least. Is that going to be fine for the AX88180 ethernet IC? Is it even going to work, connected to the STM32F7 with a memory controller configured for SDRAM?

bingo ! check that out first !