In VHDL you can't assign a 12 bit literal to a 10 bit signal or variable. So you need to either use binary, or they did recently (2008) extend the language to have variable length literals, 10x"11A", but not all tools support every 2008 feature... yes, even 12 years later.
But VHDL, like ADA, supports underscores in numeric literals, and has for a long time, so as we said above, that helps. But underscores are not supported in ALL types of lterals, so that can be confusing.
For instance, they are for integer literals. For instance (for your example):
2#01_0001_1010#
They also are for bit vectors:
B"01_0001_1010"
Oddly, underscores are not supported for std_logic_vector, and that's probably why it's rarely seen in VHDL code, as many people tend to use std_logic_vector everywhere even when using other types would make more sense.
Note that the "&" operator in VHDL alleviates all this, if you don't have access to tools that support recent enough versions of VHDL. You can absolutely use it in literals.
That would be here:
"01" & "0001" & "1010", which is easier to read.
You can then combine bases too:
"01" & x"1A" works too.
Finally, if your constants are really decimal integers but you need to set std_logic_vector, using conversion functions is a lot easier to write, maintain and read (it's unfortunate IMHO that we still see engineers manually converting decimal to binary whereas the compiler can do it for you):
std_logic_vector(to_unsigned(282, 10))
You can always define a function for this if you find it cumbersome to type:
function Dec2SLV10(n : integer) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(n, 10));
end Dec2SLV10;
Many ways to skin a cat.