Need to simulate LPDDR3

[kingkone]

Hi,

we are a very ambiguous hardware project, we set out to make hardware for OpenHD. (Realtime first person video for drones)
We have a nice SoC with a fast H.264/H.265 encoder, software work on the drivers and ISP is on the way.
But the SoC needs RAM. As I learned about DDR3 and the specifics of LPDDR3 I noticed that we need tom simulate it.

We don't have the money to get a big package like Allegro or Altium.

So do you guys have a tip for us, how to accomplish this task.
I am willing to learn and like to invest a lot of time.

I know about atlc and also got it to run but I have no way of creating the images needed for it yet.
Also i have no clue yet how to get that "open eye graph" with the tools I have so far. Can i do that with Spice aka ngspice in Kicad?
As everyone uses the of the shelf tools information on this topic is sparse.

If someone could point me in the right direction, it would be nice 

I have learned that i need to do the length matching of the 4 bytes, address and control lanes on a ToF basis.
I know that i can view the lanes separately with the respective clocks, data strobes.

Thx in adv.
Daniel

[nctnico]

You don't need to simulate it perse. Just follow the routing rules from the SoC's hardware manual and look closely at the layout for a demo board. What will be critical is length matching but Kicad should be OK for this. I don't know if you can group routing constraints in Kicad. Either way you need to layout the traces with room to add extra length. Worst case you need to check which trace within a byte group (including DQ signals) is the longest and then make the other lines just as long. Be sure to check whether you might need to compensate for package delays inside the SoC. Be prepared to make an Excel sheet to keep track of what you are doing.

[kingkone]

Thx nctnico!

>You don't need to simulate it perse.
Good to hear that.

Also yes I know that i only need to match the traces of their group, not forgetting about the DQ signals for sure ;-P
Sadly the demo boards are Allegro files and using only using DDR3, we on the other hand using a eMCP with LPDDR3 because of space constrains.
Pin-out for the different DDR modes are totally different. 

> package delays inside the SoC
good point =O

Yes KiCad can help with length matching, but not time based, have to calc that myself then. I'll will have a look DRC in KiCAD, good idea.
I took a note not make notes of it ;-P
Good to read that what i learned so far is not completely wrong. Thank you!