Dealing with interference, ground loops, decoupling and isolation problems

[mjbmikeb]

I built a capacitive liquid level sensor that works great as a main interference receiver 
I'm about to rebuild it using a lower impedance design with ground isolation - if only I had known before...

USB isn't isolated. I wonder how many Arduino users know that. A desktop computer ground is connected to mains ground, a laptop running from a plug pack isn't.

[Jimmy]

I found out the hard way

[ejeffrey]

Care to share your design?  Both the electrical and mechanical design is relevant.  It should be possible to make work even a high impedance design, although it might not be worth the effort.

[Computeruser]

>>>> USB isn't isolated. I wonder how many Arduino users know that. A desktop computer ground is connected to mains ground, a laptop running from a plug pack isn't.

True, of course. Now I thought perhaps a wired ethernet cable would provide a ground connection to a laptop, but it does not. At least I am testing at home where the network gear and cables are all commercial, so I am quite certain the ethernet is properly wired. But the laptop remains isolated when a network cable is plugged in. ... C

[alm]

To prevent ground loops, ethernet interfaces are usually (I think it's required by IEEE 802.3something) isolated through a transformer. I wouldn't count on it for safety, though. This is because ethernet cables between floors may connect different circuits at different ground potentials. This may be different for shielded versions, although I believe the convention is to only connect the shield on one side of the cable. In the case of power over ethernet, either the power should be isolated (eg. isolated DC/DC converter) or the device itself should be isolated from its environment (eg. power supply common not tied to case).

[Computeruser]

>>> I wouldn't count on it for safety, though

I do not think I implied I would rely on such a thing. I would not. I was just noting that the ground did not exist in my tests. ... C

[ivan747]

Here's a quick fix: add an optoisolator to the interface between the MCU and the sensor.

[seattle]

I built a capacitive liquid level sensor that works great as a main interference receiver 
I'm about to rebuild it using a lower impedance design with ground isolation - if only I had known before...

USB isn't isolated. I wonder how many Arduino users know that. A desktop computer ground is connected to mains ground, a laptop running from a plug pack isn't.

Being connected to a PC ground isn't at all doom for a product. Your cellphone will be able to receive signals that are 10 pico watts in power while connected to your computer. I routinely build circuits where in the input signal is just 200uV and it sits a few inches away from a 125 MHz FPGA, DDR and 480Mbps USB2.0 chip.

Do you actually care if you are ground referenced? If you need a ground, you might as well use the PC ground. If you don't need a ground (because you need to float to measure something) then you will generally use an isolated DCDC part to generate the other supply and then let that float.

On your schematics, anything sensitive connect to analog ground. Any thing with square waves, connect it to digital ground. Use a DCDC for logic if you wish, but you SHOULD use an LDO for the analog. In fact, you might cascade two LDO. This is because the PSRR of an LDO at frequencies of interest might be just 70-80 dB, and if you are wanting to take a small signal and gain it up significantly, you will very quickly be at the limit of the PSRR spec.

So, say you have 5V coming in the from the USB. That will be 4.75V worst case. Use a 200 mV dropout LDO to get to 4.5V, and then another 200 mV dropout LDO to get to 4.3V. That 4.3V signal will be pristine. Use that for the opamps. If you need a negative, use a DCDC and follow that with an LDO.

And then tie the Analog and Digital grounds together at ONLY ONE PLACE with some 0603 or 0805 resistors. Usually, the one place will be the USB connector. But there are times where you might find it is better to tie them together elsewhere. You just have to experiment and find the sweet spot.

PS. The reason a cellphone can work so well when connected to a noisy ground is because it doesn't care that the ground is boucning all over the place. As the ground moves up, the 2.75V supply moves up. As the ground moves down, the 2.75V supply moves down.

[Zero999]

So, say you have 5V coming in the from the USB. That will be 4.75V worst case. Use a 200 mV dropout LDO to get to 4.5V, and then another 200 mV dropout LDO to get to 4.3V. That 4.3V signal will be pristine. Use that for the opamps. If you need a negative, use a DCDC and follow that with an LDO.

You won't get very good ripple rejection operating a regulator near it's drop-out voltage. You'll probably do better to use one regulator to get 3.3V from 5V, or even 4V if your analogue circuits won't work that low.

[seattle]

Not true.

As long as you are outside the dropout spec, you are getting very close to specfified PSRR. PSRR is largely independent of dropout.

The problem with a single regulator is that even a low-noise LDO with an amazing PSRR at 10 Hz of -80 dB will have insufficient PSRR of -60 dB 100 KHz.

If you need 90 to 100 dB of rejection in your power supply especially out at a higher frequency, then there is no way to get it from a single LDO.

[Zero999]

Not true.

As long as you are outside the dropout spec, you are getting very close to specfified PSRR. PSRR is largely independent of dropout.

The minimum ripple valley needs to be below the drop-out voltage so if the drop-out voltage is 0.5V and there's 50mV peak of ripple, there will be virtually no ripple rejection until the input voltage exceeds the output voltage by 0.55V

[seattle]

The minimum ripple valley needs to be below the drop-out voltage so if the drop-out voltage is 0.5V and there's 50mV peak of ripple, there will be virtually no ripple rejection until the input voltage exceeds the output voltage by 0.55V

Yes, of course. If the ripple dips you below the drop out spec, then you aren't within the drop out spec and the PSRR doesn't apply any longer.

[ejeffrey]

So, say you have 5V coming in the from the USB. That will be 4.75V worst case. Use a 200 mV dropout LDO to get to 4.5V, and then another 200 mV dropout LDO to get to 4.3V. That 4.3V signal will be pristine. Use that for the opamps. If you need a negative, use a DCDC and follow that with an LDO.

Generally you will do better by having a passive filter plus an LDO than cascading two LDOs.  Often at the frequency you are interested at, an LDO has negligible power supply rejection.  Even a simple RC filter in the supply line preceding the LDO can provide reasonable attenuation, and ferrite beads can do even better.  The passive filter gives you good rejection at high frequency, and the LDO provides the DC accuracy.  You can also do better than standard regulators by building it yourself, especially if you can tolerate the loss in DC accuracy or have a post-regulation stage to get the DC level right.  Capacitance multipliers made with RF transistors and programmable current sinks an error current proportional to the input ripple are two ways to get this.

A switched capacitor voltage doubler (or inverter) is also a nice way to get a quiet supply.  The switching transients from the switched capacitor are generally much less objectionable than those from an inductor based SMPS, and because the capacitors act as current integrators, they have extremely good rejection well above their switching frequency.  You can make a very quiet low-current DC 5 V supply from USB by using a voltage doubler to get 9-10 V, a passive filter to remove the switching glitches from the flying capacitors, and a linear regulator to get 5 VDC.  Obviously you waste a lot of power, but for low noise, low power circuits this is a great solution.

And then tie the Analog and Digital grounds together at ONLY ONE PLACE with some 0603 or 0805 resistors. Usually, the one place will be the USB connector. But there are times where you might find it is better to tie them together elsewhere. You just have to experiment and find the sweet spot.

Only split the analog and digital grounds when you are desperate.  The normal advice is to connect the analog and digital grounds underneath the ADC.  Most ADCs require you to connect the AGND and DGND pins together directly at the device for optimum performance.  This works OK, but isn't scalable when there are multiple mixed signal devices.  The real advice is to divide your board into analog and digital areas and to not run any digital signals in the analog section or vice versa.  As a last resort, splitting the ground plane can help, but then as you say, you must only connect it in a single place -- usually underneath your ADC.  If you have used proper layout and kept digital devices and signals away from your analog section, this is usually not necessary or helpful.

PS. The reason a cellphone can work so well when connected to a noisy ground is because it doesn't care that the ground is boucning all over the place. As the ground moves up, the 2.75V supply moves up. As the ground moves down, the 2.75V supply moves down.

This is only half the story, and the less interesting half.  It is true of all circuits that they don't care if the entire circuit bounces up and down since voltage is only a relative thing.  The problem with a 'noisy ground' is that two parts of the circuit that are both supposed to be at ground will have different potentials due to current flowing along the path between them.  This voltage drop causes two components to see different 'ground' potentials and causes an error in the reading .  The high speed electronics in a cell phone can generate ground potential drops of 10s of millivolts across the ground plane.  The reason a cell phone (or any other highly integrated mixed signal device) can work so well in the face of all the noisy digital electronics is that the PCB is laid out carefully so that digital return currents do not run along the same path as the analog return currents, so the analog components do not see that voltage drop.

[seattle]

Generally you will do better by having a passive filter plus an LDO than cascading two LDOs.  Often at the frequency you are interested at, an LDO has negligible power supply rejection.  Even a simple RC filter in the supply line preceding the LDO can provide reasonable attenuation, and ferrite beads can do even better.

No way. A passive network cannot touch cascaded LDOs. A design exercise for you: How do you get 120 dB of attenuation at 100 KHz while passing from 0 to 100 mA. And no, ferrite beads won't do even better here. But if you wish to use those in your design exercise, go ahead.

A switched capacitor voltage doubler (or inverter) is also a nice way to get a quiet supply.

Actually, they are quite noisy, and the regulation is poor and load dependent.

Only split the analog and digital grounds when you are desperate.

and

The high speed electronics in a cell phone can generate ground potential drops of 10s of millivolts across the ground plane.

Generally no. A cellphone has at least one (sometimes more) sheets of ground plane, and these will have resistivity well under 1 mOhm/square. And peak currents today in a cell phone (not including GSM burst) are around 2.5A, spread across many supply domains. But even if you have 1/3 of that getting switched all at once, you'd still only see 1A across that very low resistance so the bounce in a properly designed cellphone will be under 1mV. Now, this is actually quite hard to measure. But if don't have this level of performance, the receiver will be desensitized. Also, ground bounce eats into your CPU voltage margin. For every mV of ground bounce you have, you need to increase your CPU operating voltage by 1 mV otherwise you'll get errors that are very, very hard to find and correct.

The reason a cell phone (or any other highly integrated mixed signal device) can work so well in the face of all the noisy digital electronics is that the PCB is laid out carefully so that digital return currents do not run along the same path as the analog return currents, so the analog components do not see that voltage drop.

And how do you think they separate these return currents? Answer: Using separate analog and digital grounds. Don't take my word for it. Go look at a phone schematic. It's not at all a "desperate" act. It's solid engineering. It is what you have to do if you want to resolve uV signals on a 2 layer board with an FPGA running at 100 MHz and a noisy 480Mbps USB connection, or if you are running on a 10 layer ALIVH board where the RF is 15 mm from the processor. And it costs nothing to do so there's really no down side to doing either.

[jahonen]

Instead of the usual speculation, I have made a real-world measurement how much high-frequency isolation slot gives a while ago:

https://www.eevblog.com/forum/index.php?topic=2315.msg50035#msg50035

It seems that the advantage of a slot is quite small (note that different level of even harmonics bias the situation), and it may even be negative due to uncontrolled capacitance between different plane sections, which will resonate at some frequency actually causing a deterioration of isolation. The separation was much larger than is usually possible for typical design so slot advantage will reduce even more. Digital signal high-frequency return currents will reside mostly directly below the actual signal due to minimization of stored energy (least inductance), assuming that there is plane available in nearby next layer.

And we should not forget that if there are cables connected to the system where different cables are at different RF-potentials (lots of split grounds), then it is almost guaranteed way to have EMC problems, mainly at emission side but immunity (AFAIK FCC does not require this, but CE does) may also be a problem. These problems may be much larger headache than isolation advantage gained by the slot. I have systematically used contiguous ground plane with a components placed properly and never had a problem with IR-drop coupled noise via GND plane (but then, I'd like to use at least 4 layer PCB unless there is a very good reason to use less).

And for final note, I once improved a D-class amplifier where manufacturer insisted on using a very complex ground split between power and small-signal side using a 2-layer PCB. Well it turned out that the original recommended strategy didn't quite work, and there was huge amount of RF noise affecting even analog performance (audible noise due to common mode emission problems, even with huge amount of Y-capacitors in each signal line). Then I decided just put one contiguous plane (this time on a 4-layer PCB) across the whole PCB, and behold, all emission problems were completely gone (no need of Y-caps anymore), in addition that audible noise was gone. So much for separated ground effectiveness.

Regards,
Janne

[ejeffrey]

Generally no. A cellphone has at least one (sometimes more) sheets of ground plane, and these will have resistivity well under 1 mOhm/square. And peak currents today in a cell phone (not

Sheet resistivity is completely irrelevant.  High speed design is 99.9% dominated by inductance.  The ground 'plane' absolutely bounces up and down locally in response to the high speed digital transitions (at least if they are ground referenced -- differential signals that are more strongly coupled to each other than the ground plane don't influence the ground as heavily)

And how do you think they separate these return currents? Answer: Using separate analog and digital grounds.

No, you segregate return currents by keeping high speed digital traces out of your analog signal area and vice versa.  At 100 MHz the return current will travel directly under the signal trace unless you put a break there.

Don't take my word for it. Go look at a phone schematic. It's not at all a "desperate" act. It's solid engineering. It is what you have to do if you want to resolve uV
signals on a 2 layer board with an FPGA running at 100 MHz and a noisy 480Mbps USB connection, or if you are running on a 10 layer ALIVH board where the RF is 15 mm from the processor. And it costs nothing to do so there's really no down side to doing either.

Multiple ground planes on multiple layers is a common and accepted engineering practice.  If you are building a 8 or 12 layer board, having separate analog signal layers with their own separate ground layers is an excellent idea.  What I was saying you should avoid is splitting a ground plane in half on a 2- or 4 layer board.  As general advice, this is completely solid.  There are a few situations when it is advisable to split a ground plane, especially with low frequency signals (where the return currents are not so strongly confined), but almost always the people asking about this have made serious mistakes in their layout and are trying to put a band-aid on it. 

[seattle]

Instead of the usual speculation,

Who in the world is speculating here? I've been shipping cellphones since 1992. Hundreds of millions that I or my team have worked on are out there and working. I'm telling you exactly what a roomful of engineers at any big cellphone company would tell you if someone asked "how do I get analog and digital working well together on a board?" It's not like this is controversial, either.

I appreciate your experiment with that amplifier, but the engineers working on stereo equipment are miles away from pushing the state of the art. Today, cellphones are sticking a dual core 1.5GHz processor with a 533 MHz DDR bus 20 mm away from 17 receivers: Quad EDGE, penta-band UMTS, BT, two wifi bands, NFC, BT and GPS. There is nothing more demanding out there today frankly.

And alas, I see you skipped your homework assignment about a passive circuit attentuation at 100K

Sheet resistivity is completely irrelevant.  High speed design is 99.9% dominated by inductance.  The ground 'plane' absolutely bounces up and down locally in response to the high speed digital transitions (at least if they are ground referenced -- differential signals that are more strongly coupled to each other than the ground plane don't influence the ground as heavily)

But you are missing the point. A ground plane BY DEFINITION doesn't have significant stray inductance. Sure, the traces atop of them will if the designer wants them to. But the ground plane itself does not. You can look at the formula

If you want to convince me otherwise, then find a complicated schematic on the web, or an app note from ADI or TI or STE, where they are doing things as you describe and connecting the analog and digital together and treating it all as one. I'm not saying what you are saying can't be done. I'm just saying it goes against what the entire electronics industry has been doing for decades.