I have designed (circuit and layout) a few hundred PCBs, including many TTL based PCBs with 20-100 chips, so I have suitable experience to answer this.
I suggest that the rationale was approximately the following...
<tldr> The chips will be arranged in a grid pattern, VCC and VSS are required at every chip, and what matters in EMC is loop area.</tldr>
The best solution always was a power and ground plane, (which cuts loop area to just about nil) but not all of the jobs we did could afford the extra layers. Mostly power and ground were grid routed horizontally and vertically. That means multiple routes for power - a chip near the centre of a grid has power and ground routed to both chips at either side, and above and below.
This was assisted greatly by most of the chips being about 14,16 or 20 pins, similar physical sizes. Once you have that grid routing in place, decouple capacitors could be placed straddling each of power and ground. Yes, it is required that the supply feed be low impedance, and that low impedance was facilitated by decoupling capacitors. But really, in the bigger scheme of things, minimizing that loop area was more important. And that loop area could not really be made a lot smaller than each of the chips - and when that becomes apparent, it really means that the position of the power supply pins is really less important - it is better to get them as far out of the way as possible, so there is more opportunity to connect signal pins directly to each other, and often those signal connections might be from one pin on a chip to another pin on the same chip - having the power connections out of the way gave more opportunity for those signal connections to be better optimised.
<philosophy> I hope with this different way of analysing the problem, you can see why the choice was (and still is) the best, logical, solution.
If designs were such that connections between pins on the same chip were much less likely than connections between different chips, then argument for shifting power pins out of the way holds less weight. However, the nature of logic chips is such that gate-to-gate connections are more common. Now when to reconsider this in terms of say, Microprocessors or FPGAs, then would connections would rarely be made between pins on the same chip, unless we were grounding a mode pin or something. With those devices, the loop area rationale is just as important, but there is no solid reason to "get the power pins out of the way of the signals", as the tracks are as likely to run away from the device as across the device. There is also less opportunity to grid route power to dis-similarly sized devices. There is also more opportunity for devices to be used in PCBs with just a few chips, perhaps even just one or two. With those factors in mind, it becomes more prudent to design a pinout that places power and ground close enough together so that a decoupling capacitor can easily be placed between them, which was the point-of-view of the original post. But logic chips, TTL? Yep, corner power pins were the best tradeoff, chosen by engineers with far more practical knowledge than we could ever hope for </philosophy>
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