What is maximum frequency of sinus signal that can be generated using Arduino R4

[FlyingDutch]

Hello,

I cannot find in datasheet what is maximum frequency of sinus signal generated from 32 samples using internal DAC in  "Arduino UNO R4 Minima". I wasn't able to find this information on Arduino website, nor in Renesans manual of MCU R7FAM1AB3CFM. Found information that  max. square signal frequency is about 52 KHz.
Could somebody give me estimated max. frequency of sinus signal generated from min. 32 samples.

Thanks in advance and regards

[pcprogrammer]

I cannot find in datasheet what is maximum frequency of sinus signal generated from 32 samples using internal DAC in  "Arduino UNO R4 Minima". I wasn't able to find this information on Arduino website, nor in Renesans manual of MCU R7FAM1AB3CFM. Found information that  max. square signal frequency is about 52 KHz.
Could somebody give me estimated max. frequency of sinus signal generated from min. 32 samples.

Look in the datasheet what the maximum update rate of the DAC is. In other words what the maximum sample rate can be. Then divide this by your 32 samples and you have your answer.

Also depends a bit on how you write to the DAC and how fast the CPU is. When using DMA, if available, it can be faster than using a software loop to write the samples.

[Psi]

If you're after speed rather than accuracy you might also consider creating an artificial PWM based DAC using a timer.
I'm not sure what speed that chip can do timer wise but it has a 64mhz clock. So it can likely clock a timer at 64mhz.
Limit the timer count max to 32 and your down to a 2mhz cycle.

[PCB.Wiz]

I cannot find in datasheet what is maximum frequency of sinus signal generated from 32 samples using internal DAC in  "Arduino UNO R4 Minima". I wasn't able to find this information on Arduino website, nor in Renesans manual of MCU R7FAM1AB3CFM. Found information that  max. square signal frequency is about 52 KHz.
Could somebody give me estimated max. frequency of sinus signal generated from min. 32 samples.

You may need to experiment, to see what can be done.
Depending on the internal DAC design, you might be able to go (much) faster than the paper values.

eg on a SiLabs MCU DAC, I've managed to directly INC/DEC the DAC register at up to 36MHz, which is way above their paper rate, but it keeps inside their slew rate spec, because only one LSB step changes at a time.
It is also possible to generate sines faster than their paper rate, provided you keep inside the slew rate.
A 32 step sine has only a small step change.

The Renesas DAC data says
Conversion time - - 30 μs    -> 1041.666667 Hz max at your 32 samples per cycle.
I cannot see a slew rate number.

So you need to experiment, ie write a tight loop that dumps your table to the DAC and check it works at 30us per update, then speed that up until it breaks.
If it appears to be slew rate limited, you can generate a smaller amplitude sine and add external gain to nudge the rate up faster.

Addit:  Google finds this
https://forum.arduino.cc/t/arduino-uno-r4-dac-speed/1177741/8

There, scopes shots give you exactly what you need

One example has updates at 588kHz and shows a DAC slew rate of about 5V in 2us or 2.5V/us
You can generate a triangle wave of roughly 5V amplitude up to 250kHz, at that top rate, actual values depend on slew rate, not DAC precision.

A sine wave must fit inside that triangle, so you could choose a lower amplitude at 250kHz or a lower frequency.

This comment in the code examples given is in one example

Code: [Select]

  *DAC12_DADR0 = loop_count++;         // DAC update            - takes c. 210nS  - DAC ignores top 4 bits
That comment suggests ~150kHz for your 32 sample sine.
For DDS you need to increment and table lookup, so if we guess that takes 312ns, you hit 100kHz ballpark for your 32 sample sine, using 100% MCU bandwidth.
Looks like you hit a code speed limit just before you hit the DAC slew limit, if chasing full swing Sine out, for your 32 steps.
Fewer steps will hit the slew limit first.
 

[radiolistener]

square signal frequency is about 52 KHz.
Could somebody give me estimated max. frequency of sinus signal generated from min. 32 samples.

Maximum sinus frequency is square wave signal which requires min 2 samples.
You mentioneds that max square wave is 52 kHz which is for period 2 samples.
So the max frequency with 32 samples will be 52 * 2 / 32 = 3.25 kHz.

[FlyingDutch]

...
Look in the datasheet what the maximum update rate of the DAC is. In other words what the maximum sample rate can be. Then divide this by your 32 samples and you have your answer.

Also depends a bit on how you write to the DAC and how fast the CPU is. When using DMA, if available, it can be faster than using a software loop to write the samples.

Hi,

there is lack of this information (maximum data rate) in DAC datasheet. If I had this information, I wouldn't ask the question on the forum.

Best Regards

[westfw]

there is lack of this information (maximum data rate) in DAC datasheet.

huh?
Right there in Table 48.51 "D/A conversion characteristics):  Conversion time: 30us (max)
That implies a a minimum max frequency for 32 steps of about 1kHz...


(ok, the chapter about the DAC is pretty sparse.  I don't even see info on clocking, there.)

[pcprogrammer]

The Renesas DAC data says
Conversion time - - 30 μs    -> 1041.666667 Hz max at your 32 samples per cycle.

The datasheet states a MAX conversion time of 30uS which means worst case sample rate to be 33,333kSa/s. There is no minimum specified so the sample rate can be much higher.

The datasheet also specifies a resistive and capacitive load. Minimum resistive load is 30k Ohm and the maximum capacitive load is 50pF. This is also of influence on the slew rate, and thus max obtainable output frequency.

Maybe there is more information to be found in the other manuals for this MCU. See: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4m1-32-bit-microcontrollers-48mhz-arm-cortex-m4-and-lcd-controller-and-cap-touch-hmi#documents

[westfw]

The datasheet states a MAX conversion time of 30uS which means worst case sample rate to be 33,333kSa/s. There is no minimum specified so the sample rate can be much higher.

What technology DAC has varying conversion times?  Usually you're talking just some sort of resistor ladder, not even clocked.  (And I don't see anything in the datasheet about any sort of clock provisioning for the DAC...)
OTOH, given a 12bit DAC, you may get conversions to 8bit accuracy faster than the max time, I guess.

[PCB.Wiz]

What technology DAC has varying conversion times?  Usually you're talking just some sort of resistor ladder, not even clocked.  (And I don't see anything in the datasheet about any sort of clock provisioning for the DAC...)
OTOH, given a 12bit DAC, you may get conversions to 8bit accuracy faster than the max time, I guess.

See my reply and links that include scope shots (one added below) and sample code in #3

You can update the DAC register much faster than 30us.

The missing parameter that matters is slew rate, other vendors give this.

[pcprogrammer]

In the hardware manual there is mention of "tDCONV" that specifies the delay after writing to the DAC data register, but there is no value given for it. 

So to know the absolute maximum speed at which the DAC can reliably be written just do a test with a fast scope and a single capture of a transition from 0 to 4096. This will show how fast the signal can change and be a measure for the maximum useful sample rate.

[westfw]

Yeh; sucky datasheet.  There aren't enough details in the DS of what might affect tdConv, either.  The "block diagram" is full of info on the "prevent interaction with ADC" logic, but shows the DAC itself as a monolithic empty box.   Grr.

just do a test with a fast scope and a single capture of a transition from 0 to 4096.

Although, if the conversion time is dependent on how big a jump is made, then the OP's desire for a 32-step sine wave is likely to able to go faster...


Time for experiments, I guess.

[PCB.Wiz]

In the hardware manual there is mention of "tDCONV" that specifies the delay after writing to the DAC data register, but there is no value given for it. 

Even that is simplistic.
The waveforms and tests I linked already in #3, show there are two delays.
A propagation delay from Write until the register value is applied, and the output starts changing, PLUS a Slew Rate defined delay, until that value settles.
Hopefully the propagation delay is consistent, and the slew rate means the conversion settle time varies with step size.

A sine wave model table at higher speeds, could use that slew info to give better values ?

The code used in test #3, sets the control register once, and can continually update the DADR0

Code: [Select]

*DAC12_DACR     = 0x5F;                // D/A Control Register -
..
void loop()                            // Total loop()          - takes c. 667nS per loop; or c. 750nS per loop with if() exit
  {
  *PFS_P107PFS_BY = 0x05;              // Set D7 output high    - takes c.  83nS
  *DAC12_DADR0 = loop_count++;         // DAC update            - takes c. 210nS  - DAC ignores top 4 bits
  *PFS_P107PFS_BY = 0x04;              // Set D7 output low     - takes c.  83nS
  } 

[radiolistener]

I don't understand what is confusing you?
Since it can produce max 52 kHz with 2 samples per period, it's pretty simple to calculate max frequency for 32 samples per period:

52 * 2 / 32 = 3.25 kHz