The main part won't work. You can't just transcribe the circuit from logic gates to Verilog and expect it to work.
Correct way to describe a D-latch would be something like this:
`timescale 1ns / 1ps
module d_latch(
input clk,
input reset,
input CE,
input D,
output Q,
output NQ
);
reg V;
always @(posedge clk or posedge reset)
begin
if (reset) begin
V <= 1'b0;
end else if (CE) begin
V <= D;
end
end
assign Q = V;
assign NQ = !V;
endmodule
You can adjust the polarity of the reset signal, or remove the clock enable (CE) signal if you want.
But the main thing here is to have a register value ("reg V") that represents the "stored" quantity. In the real world it happens though an essentially analog feedback process, which can't be replicated reliably in digital logic (especially in FPGAs).