Reminds me the My Big Fat Greek Wedding movie. The father loved to explain the greek origin of words. ;-) Great movie.
Hope you've enjoyed, I'm more of scifi, action, thriller kind so still need to watch the whole movie and not only in bits.
What do you mean by collapsing multiple operations in the same clock cycle? Just doing more complex logic function between the register stages? If so, it is still 100% synchronous.
Yes, you got me there. I also wouldn't use handshakes/acknowledgement, better to go with synchronous interfaces where possible.
There is an under-referenced technical report by a student of Prof. Gajski, about Modeling custom hardware in VHDL. It describes FSMDs (Finite State Machines with Datapaths) that using asynchronous handshakes. However, never used these techniques, they might be ill-suited to FPGAs.
There is also a well-known project on an asynchronous toolchain by Univ. of Manchester. And once there was an asynchronous ARM, AMULET (?), don't know if this went into production.
A Greek research institute had also made an asynchronous DLX (ASPIDA) synthesizable core. The prime minister at the time paid them a visit or so at an exhibition.
That's all.
Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com