VHDL problem

[Harvs]

I haven't used an FPGA in anger for about 12yrs now, so this is probably an obvious question.

I'm using Lattice Diamond with the Lattice synthesis engine, and Modelsim for simulation.

This is a basic 8bit serial transmitter, I'm sure it's not the best way of doing it, but anyway.  There's a top level file that just wires up the clock and the DATA to a constant vector, then taps the outputs out to pins.

It simulates fine in Modelsim, with no warnings etc.

In Diamond it gives a synthesis warning of:
serial.vhd(43): WARNING: Bit 10 of Register \tx_unit/shift_reg is stuck at One

The output of the device gives the serial clock enable pulse, but the tx line is dead as expected from the warning.

I've got no idea, other than maybe Lattice doesn't allow you to initialise vectors without a reset?  But I never had this problem with Xilinx years ago and can't see why it would be a problem?

Code: [Select]

library ieee;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;

entity serial_transmitter is
port(
CLK10MHZ: in std_logic;
DATA: in std_logic_vector(7 downto 0);
LOAD: in std_logic;
TX: out std_logic;
BUSY: out std_logic);
end serial_transmitter;

architecture serial_arch of serial_transmitter is
signal serial_clk_div : unsigned(6 downto 0) := (others=>'0');
signal serial_state : std_logic_vector(10 downto 0) := "00000000001";
signal shift_reg : std_logic_vector(10 downto 0) := (others => '1');
signal txer_busy : std_logic;

begin

process(CLK10MHZ)
begin
if(CLK10MHZ'event and CLK10MHZ='1') then
shift_reg <= shift_reg;
txer_busy <= '1';
if(serial_state(0) = '1') then
if(LOAD ='1') then
serial_state <= serial_state(9 downto 0) & serial_state(10);
shift_reg <= "0" & DATA & "11";
else
txer_busy <= '0';
end if;
else
if(serial_clk_div = "1010111") then
serial_state <= serial_state(9 downto 0) & serial_state(10);
shift_reg <= shift_reg(9 downto 0) & '1';
serial_clk_div <= "0000000";
else
serial_clk_div <= serial_clk_div + 1;
end if;
end if;
end if;
end process;

BUSY <= txer_busy or LOAD;
TX <= shift_reg (10);

end serial_arch;



[Harvs]

Ok to answer my own question.  Yes initialization matters...

You use the GSR_NET signal to provide an async reset to everything, and then all is well.

edit: typo