Verilog - Connect non-top level module to pins directly

[pigtwo]

Hello everyone!

I have a hard to google question so I'm hoping someone here might know.

I'm working with a project in Verilog and I was wondering if there was a way to have a non-top level module have some of its inputs/outputs connect directly to a pin without going through the top-level module. 

I hope that made sense, it's kind of hard to explain.  I'll try to explain more in an example.  Say I have a module that just blinks a LED and I don't want this to be done in the top level module.  Is there a way that I could have that module connect directly to a pin without it going through the top level module at all?  So in this(extreme) case that module would actually have no connection to the top level module.

I'm using Quartus II if that helps. 

Thanks!

[marshallh]

Nope

[pigtwo]

Damn

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[miguelvp]

You can always make a block diagram/schematic file top level. And then create a symbol file from your Verilog modules.
Insert the created symbol in your bdf file and connect it to a pin.

Insert your previous top level as a symbol in there too so it can do what it needs to do.

[mrflibble]

You probably can do it in Quartus, but it will no doubt be more trouble than it's worth. You can do it in ISE, and I know it is more trouble than it's worth there. You would have to muck about with putting constraints on signals to make sure they are not optimized away and are connected. Incidentally, do the altera tools have the equivalent of fpga editor (a la xilinx)? Reason I ask, you can also do this "connect to pin" business using fpga editor. And again, for the job of connecting a non-top level signal to the io pins this is more trouble than it's worth.

So the short answer is already given by marshallh. 

[AndyC_772]

I often allocate some top level pins as test points for exactly this reason. Each lower level component has some test point outputs, which I map to the 'real' TP pins as and when there's something I need to debug at the lower level.

There's no shame in including some test & debug capability as part of your design, and you can always just program the external TP's to drive 0 in the final design if you don't want to expose any of the inner workings of your logic through them.

[pigtwo]

That's what I was expecting.   I was hoping there would be like a keyword you could add or something.   

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