I thought I'd post an update, as I managed to obtain and get a 10 MHz oscillator working on my board. The pins necessary for crystal operation are not exposed, but the XIN pin can be used for a CMOS output oscillator, and this is exposed via the ICSP header. As I was feeling lucky, I bought an unknown oscillator off amazon - which turned out be sine output. After some trial and error, I found that this did in fact work with the MCU if AC coupled to the XIN pin, and setting XOSCCTRLn.XTALEN = 1 (presumably setting XTALEN enables a bias network internal to the MCU).
The experiment entailed inputting the 10 MHz clock, and routing the clock to a) a PLL and setting various ref frequency dividers, and multipliers to yield 200 MHz which was used to clock the input capture TC peripheral, and b) a /128 divider and routing the 78 kHz pulses to the input capture pin, and logging the timestamps, which could be used for analysis. The resulting analysis should represent the frequency stability taking into account the timer resolution and the PLL performance only.
As can be clearly seen, the higher the ref frequency, the better the PLL performance. I wasn't expecting 5 MHz to work, as it is significantly out of spec for the ref frequency, but it does work and gives better performance than 2.5 MHz. I don't know why the 1.25 MHz curve has a different shape to the others. I repeated this measurement several times, thinking it was an undetected data corruption issue (e.g. lost samples), but it is a consistent finding.
For context, the performance arising from the 5 MHz line represents a standard deviation of the timestamps of approx 0.8 clock cycles (4 ns). For the 39 kHz ref requency, the timestamp precision is about 2 orders of magnitude worse, unless measuring very short intervals (< 1 ms).