STM32U5 announcement, and a question about static power

[mark03]

So STMicro announced their new STM32U5 low-power MCUs this week, the apparent successor to the popular STM32L4 (and L5) series.  No real data yet, but the headline power numbers seem impressive.  They claim 19 uA/MHz in active mode, which is almost exactly half of that for the STM32L4.  The parts also clock up to 160 MHz, vs 80 or 120 MHz for their predecessors.

The STM32U5 is fabbed at 40 nm.  I guess the STM32L4 was 90 nm?  I am curious as to why there doesn't seem to be a static/dynamic power tradeoff like there is for FPGAs.  Is this because the silicon area is a lot smaller?  Or it is just cleverly hidden somehow?

[bob91343]

By static power I think you mean the standby, or idle power consumption.  The oxymoron 'static power' made me smile.

[mark03]

Well, it does have a reasonable / intuitive definition.  Dynamic power is power dissipated through CMOS transitions; static power is leakage when all clocks are stopped (no transitions).

[SiliconWizard]

By static power I think you mean the standby, or idle power consumption.  The oxymoron 'static power' made me smile.

I think you didn't understand what the OP was exactly asking.

Anyway, of course those are best case figures. Actually, for the L4, the lowest figure was 28 uA/MHz. This is for the lowest power of the series, but the 19 uA/MHz figure is also the absolute lowest for the U5. That's not half the power. More like 70%.
https://www.st.com/en/microcontrollers-microprocessors/stm32l4-series.html

The L4 series is indeed fabbed on a 90nm process at TSMC.

One big difference with FPGAs are all the power saving features of such MCUs. To get to such low static power, they have ways of shutting down many blocks inside the IC. Even the pretty impressive figures in "active mode" are given with many things powered off. There are usually no such features inside FPGAs. No way of selectively shutting down whole blocks. For one thing because FPGAs are entirely generic so it would be difficult to implement that - what exactly could we selectively shut down or not - and another is probably that there's little demand for that yet.

Another difference is FPGAs are mostly made of SRAM. High-speed SRAM. It's very hard, AFAIK, to implement such high speed SRAM with ultra low static power. They tend to have significant leakage.
(There are some exceptions with flash-based FPGAs, such as Actel parts, the Igloo series have nice static power figures and can be put in "flash freeze" mode. But those are exceptions.)

[LostTime77]

ST has been using 90nm for all of their STM32 except for the H7, which uses 40nm as far as I am aware. This is the first time one of their main stream chips made the jump to 40nm. The H7 is a bit niche in my eyes. I used to be involved with the ST roadmaps a few years ago and it always baffled our team as to why ST was still making new chips on 90nm instead of a smaller node. My CTO made the comment to one of the ST reps at one point: "90nm? Isn't that like 2005?". I am finally glad to see the U5 announcement. Our team was made aware of this chip in 2017 and it was supposed to launch in 2018, but out came the L5 series thereafter.

To me, ST just obsoleted their F4 series. Why would I buy an F4 over one of these besides legacy? Keep in mind its an M33, which I believe is 25% more efficient clock for clock over the M4? That would put its equivalent speed to 200MHz at an M4 level. More RAM / flash, more updated peripherals, 'way' better power consumption. The U5 finally brings the ULP lineup up to snuff with competitors such as the NXP kinetis and LPC5500 series. It's taken ST more than half a decade to get their ULP lineup into the 150MHz range. The only benefit an F4 has over a U5 for newer designs would be if I needed high speed USB or ethernet, which I think the F4 provides. Even then, I am probably going with an F7 or H7. The F1 - F4 series are just based on really old ST technology.

The L5 series is pretty limited. The U5 basically melds the L4 and L5 together giving us USB device & host with USB C & PD support. Kind of odd having USB C support & USB OTG on there, but they did that because they don't currently have any dedicated IP to handle host and device without OTG, so they just slapped what they had in there and called it a day. They added more timers, gave us some better analog peripherals, etc.. I would like to see a higher clock speed in the ULP series and HS USB support + ethernet, but they should get there eventually.

[LostTime77]

In ST's situation, it is a case of still being best in class at 90nm comparatively. They have really been able to squeeze out low static current in those stop modes for the L series devices. Active current (with linear regulators) is at the 100uA / MHz class, which still beats quite a few chips out there. We can almost halve that using a switcher. I don't think it gets down to PSOC6 levels or maybe even LPC5500, but its a multiple of 2 or 3 compared to an order of magnitude. I was in the ultra low power consumer electronics field (digital watches) and deep sleep current mattered a lot more then run current. It's all about going into run mode and switching back to deep sleep as fast as possible to optimize the time spent at that mode. ST is able to continue to squeeze current and fit what they need using a 90nm node, so there is not a huge pressure to move nodes and they can do it at their leisure. I am seeing it more and more, but I feel ST is the one really pushing the MCU game forward compared to other companies. They come out with new chips every year. Energy micro (SiLabs) used to be competitive several years ago, but now they have dropped out of the performance mainstream MCU game. Infineon and TI, I consider jokes, and NXP has some good ideas, but they are trying to bury the Kinetis series by hiding it in the background on their webpages now. NXP has been "launching" the LPC5500 and chips in the i.mx RT range for what 2 or 3 years now and still can barely get them out there? Right now, I think the game is between ST, NXP, and maybe Renasas, but ST is really putting out some bangers. Also, this is all in reference to Arm Cortex M, not other cores.

I am not saying active current doesn't matter, but I can only imagine what these smaller nodes can accomplish. Ambiq I believe is at 22nm with their Apollo 4. I have used their chips in the past, but I don't really consider them or their company useful as an MCU vendor anymore. Maybe some do, I don't. The information and purchasing of their chips went into hush hush mode once they really started showing the fact they were owned by Fujitsu. I like chips that we can just go to mouser or digikey and purchase in single quantities. Ambiq has the best active current in the industry with their newer chips. I think ST and competitors will get there eventually without playing "games" and provide many skews of chips instead of being one trick bands. Fun fact: ST was eyeballing a purchase of Ambiq at one point in time, but when asked they basically said this: "Their whizbang tech doesn't really have a future and we will be there (current draw) in a few years anyways without resorting to exotic techniques". I fully agree with ST's position on that one, because I don't think the technology has a future either. They are able to cash in for about a decade, but that tech will most likely hit a speed bump and mainstream tech will race by it.

[mark03]

Well, the reason I stick with ST is that they still document their parts in good detail, and while they certainly promote their own driver library, they don't act like you're a weirdo if you choose to write your own from scratch.  I am increasingly getting the vibe from other vendors that if you don't use their libraries, you are on your own and any undocumented behavior is your own fault.  I will go with whichever company has the best documentation and "reasonably competitive" parts.  ST's documentation is pretty bad, but still better than almost everybody else.  Sign of the times.

L4 were my favorite parts due in part to the DFSDM (hardware CIC filter) and the fact that I do a lot of DSP stuff.  I am quite curious to see what the new and improved "MDF" (multifunction digital filter) brings to the table in the U5 series.

[SiliconWizard]

In fact, the L4 has had little competition in terms of performance/power consumption ratio. There are only very few out there that do better. Also looking forward to the U5.

Also take what blueskull said in consideration. As I also said in another thread, CMOS process nodes with available embedded Flash are few and hard to come by once the nodes shrink. And it becomes pretty hard as he said to design good analog blocks at the finer nodes.

Another point is you don't necessarily gain much from using finer nodes for "small" MCUs. Unless you design parts with VERY few IOs, the number of pads will limit you - so that your die would actually have a lot of void. You may fill this void with logic/memory, but then you're designing something else, that will draw much more power. I remember we had a similar discussion on process nodes a while ago. Not only 90nm is certainly not outdated, but going for finer nodes for no technical reason other than it's newer doesn't make any sense except pure marketing.

[mark03]

Another point is you don't necessarily gain much from using finer nodes for "small" MCUs. Unless you design parts with VERY few IOs, the number of pads will limit you - so that your die would actually have a lot of void. You may fill this void with logic/memory, but then you're designing something else, that will draw much more power. I remember we had a similar discussion on process nodes a while ago. Not only 90nm is certainly not outdated, but going for finer nodes for no technical reason other than it's newer doesn't make any sense except pure marketing.

This raises an interesting question---is MCU revenue sufficient to keep these old fabs running, or will we eventually be forced onto newer process nodes, potentially losing some of the advantages that came with larger feature sizes?

What about FRAM (or was it MRAM)?  Wasn't that on track to replace flash eventually?

I have to admit, the extra SRAM in the 40- and 28-nm parts is really nice.  I've never been able to imagine what I would do with 1 Mbyte of flash, but 1 Mbyte of RAM?  Yes please!

[SiliconWizard]

Another point is you don't necessarily gain much from using finer nodes for "small" MCUs. Unless you design parts with VERY few IOs, the number of pads will limit you - so that your die would actually have a lot of void. You may fill this void with logic/memory, but then you're designing something else, that will draw much more power. I remember we had a similar discussion on process nodes a while ago. Not only 90nm is certainly not outdated, but going for finer nodes for no technical reason other than it's newer doesn't make any sense except pure marketing.

This raises an interesting question---is MCU revenue sufficient to keep these old fabs running, or will we eventually be forced onto newer process nodes, potentially losing some of the advantages that came with larger feature sizes?

90nm is certainly not OLD stuff yet. Sure is enough demand for now. Small/low power MCUs are in increasing demand. And finer nodes are much more expensive, which can make them not an option depending on the market. (The finer the node, the more chips you need to sell to be able to make it profitable...) Your question is kind of recursive in a way - as long as there is a technical need for them, those process nodes will be available. Sure as time goes by, MCU vendors are bound to make their designs evolve so as to accomodate the finer nodes though - we're already seeing that - so the older nodes will progressively vanish. But not entirely. You can still find 350nm nodes, and even 600nm for some specific applications (maybe even larger, but I have no example in mind.)

What about FRAM (or was it MRAM)?  Wasn't that on track to replace flash eventually?

The process for FRAM is much more expensive per bit than Flash. TI has managed to simplify the process and make it doable to manufacture MCUs with embedded FRAM on the same die (see the FRAM MSP430 series), but the amount of FRAM available on those is still pretty limited. It's still nowhere close to replace Flash AFAIK.

Intel is still actively working on MRAM though. I have no clue what's the current state of affairs though, and how close it could be to ever replace Flash. Or even DRAM, as was their intention.

[LostTime77]

Take a look at the Apollo4 that is now listed on Ambiq's website. The NVM and RAM in that thing is crazy. It's using MRAM, and I think it has like 1MB <- BYTE, not bit. I have worked with Ambiq on a company level before, and they are always trying to jump on technology bandwagons, despite making some very, what I consider, amateurish design decisions in their peripherals.

[SiliconWizard]

Take a look at the Apollo4 that is now listed on Ambiq's website. The NVM and RAM in that thing is crazy. It's using MRAM, and I think it has like 1MB <- BYTE, not bit. I have worked with Ambiq on a company level before, and they are always trying to jump on technology bandwagons, despite making some very, what I consider, amateurish design decisions in their peripherals.

I seem to recall your post was a lot more detailed and you edited it to remove most of it. Your call, it was interesting IIRC.

Ambiq is currently using "breakthrough" technology that can't really be compared with anything else at the moment. To achieve the lowest active power on the market (that I know of), they use subthreshold logic. The principle is certainly nothing new, but they were the first to manage implementing a fully and reliably working 32-bit MCU using it. Let me know if you know of any other vendor that makes subthreshold MCUs.

I've used the Apollo (1) when it came out. Although certainly a bit limited peripheral-wise, it was easy to use with impressive power draw figures. At the time, it was unmatched, although conventional tech has progressed enough since then that the active power of the Apollo 1 (~30uA/MHz) is nothing *that* impressive now. (ST manages to do it, but it didn't AFAIR when the first Apollo came out.)

The Apollo 3 has a figure of 6uA/MHz active current. That's crazy low. And it has a pretty reasonable set of peripherals.
The Apollo 4, which is announced but not out yet (AFAIK), gets down to 3uA/MHz (I'll believe that when I see it though!) of active current and a pretty generous amount of internal memory and set of peripherals. I'll certainly evaluate it when it's available.

But although there are some papers about it, I'm still curious how reliable this subthreshold tech really is in harsh conditions...

[LostTime77]

Yes, I edited my reply, because it was a rant into how my boss and I had a big hand in how the peripherals in the apollo series were implemented in terms of "steering" them in the right directions.. and not so much talking about the chip, power consumption, etc.. More of a salty rant of how Ambiq is very amateurish and they think they are the ones "doing peripherals right", when it turns out its very "cute" how they think that.

In terms of sub threshold logic reliability, we adamantly went back and forth with Ambiq, because we were the first users of the chips (Apollo 1/2) in which they would be placed a few millimeters away from noisy mini stepper motors. They of course assured us that they "did all the testing", and their sub threshold logic had "zero reliability issues" and would perform exactly like standard tech. If you work with the guys from their company (not just engineers, but high level CTOs, etc..), they are an extremely cocky bunch, who think they are all that in silicon design. Cue how we literally threw out their chips from usage in our designs, because of how amateurish some of the peripheral designs were... they went as far as to put custom bitbang modes into their timers for our stepper motors. They then then thought themselves stepper motor experts and proceeded to almost give away proprietary information about our very niche stepper motors to competitors. The stepper motors we made required custom drive waveforms and were in no way standard. I could go on and on about this story.. but I will stop myself there. ANYWAYS.. back to the EMC issue: They were cocky about it being a perfect technology to us and then the release of their Apollo 2 and 3 were pushed back 6+ months, because it turns out they had to "run extra testing" on the chips to validate them. I believe that the tech is very susceptible to EMC above and beyond "standard tech", and they were trying to cover the testing up, so they could get a product contract with us.

What other chips are using sub threshold? I can't say anything for certain, but I believe Epson and Renasas might have some sub threshold MCUs.

Also.. I am not under NDA with any of those vendors anymore and have since left that particular company. All I can tell you about is some of the stories with these vendors and the stories are not current or would have any effect on their current products. I do still hold on to information that 'could' reveal information on current or future vendor products that I will not reveal, even though I am not under NDA. I worked with many vendors: SiLabs, ST, NXP, Ambiq, SiFive, etc..

[Debugging]

One disappointment is the lack of an QFP32 version for U5.

[AndyC_772]

Rated for a die temperature up to 130 deg C, though