STM32H747 clock configuration.

[luiHS]

Hi.
I haven't worked with STM32s for a long time, I opted for NXP (Kinetis and i.MX), but now I have to use an STM32H747 because it is the only microcontroller I have found with MIPI DSI and hardware JPEG decoding.

The problem I have is with the clock configuration, although STM32CubeIDE brings many source code examples, none have been created with Cube, so I have no reference of what values ​​to configure in the clock.

What I have done is edit an example source code and see in the source what values ​​it has configured for the clock, they are the ones that I attach in the screenshots.

The problem is that after configuring those values, it gives me errors, indicating that some resulting values ​​exceed what is expected, however in the source I use this configuration they give me those values ​​as correct.

Specifically, it warns me of these errors:

1.- The frequency of 5Mhz when applying the PLLM /2 divider exceeds the valid value between 0.95Mhz and 2.1Mhz
2.- The PLLN multiplier at x160 gives a value of 800Mhz, when it is allowed between 192 and 432Mhz.
3.- The PLLP a /2 divider gives a frequency of 400Mhz, when what is allowed would be between 24 and 216Mhz
4.- The PLLQ a /4 divider gives a frequency of 200Mhz, when it should not exceed 75Mhz
5.- PLL QCLK is 200Mhz when it should not be higher than 75Mhz
6.- APB1 is set at 100Mhz, when it should not be higher than 54Mhz.

I don't understand what happens, all these PLL configuration values ​​I have taken from one of the example sources that the STM32CubeIDE brings.

The only thing I can think of for now is that this microcontroller has two cores, a Cortex M7 at 480Mhz, and a Cortex M4 at 240Mhz. It could be that I am configuring the clock of the Cortex M4 and that is why it does not accept these values ​​that exceed what is expected, but I do not see how the core to configure would be selected, if that is possible, in the Pinout & Configuration section I only see Cortex M7.

If I press the option for the IDE to automatically resolve the conflicts, it configures me some values ​​that leave me a SYSCLK value of 96.895Mhz, much lower than the 400Mhz at which it should work.

[luiHS]

Sorry, I made a mistake, I had selected a STM32F769 microcontroller instead of a STM32H747.
I do not see here the possibility of deleting the post.

[luiHS]

 
I have already configured the correct microcontroller, a STM32H747 and with the above values it no longer gives errors.

What I don't understand is why the PLL appears three times, PLL1, PLL2 and PLL3. I could understand that it appeared twice, once for the Cortex M7 and another for the Cortex M4, but I don't know why it is there three times.

I still don't know how to handle these dual core, it is the first time that I use a microcontroller with two cores, now I only want to use the Cortex M7, I don't know if the Cortex M4 has to be disabled or that does not matter. I see that in the project two folders are automatically generated for the M7 and M4, and each one with subfolders for independent sources, all this is new for me.

[Siwastaja]

Really, read the manual. It's all explained surprisingly clearly there. Three PLLs exist because you may want to use PLLs for something else than just the cores, for example ADC, external clock outputs...

Once you read the manual, you don't need the Cube point/click interface at all, or at least you understand what everything means there.

The clock tree is complex, but it's no more difficult than driving in a city with multiple intersections. You create different clocks then choose which peripheral (or CPU core) uses which clock. There are tables of different "speed limits". Some PLL internal steps have minimums and maximums, and each peripheral has some maximum.

[rounin]

What I don't understand is why the PLL appears three times, PLL1, PLL2 and PLL3. I could understand that it appeared twice, once for the Cortex M7 and another for the Cortex M4, but I don't know why it is there three times.

On the H750 I use one PLL for the core+most peripherals and one PLL for the CAN controller, so I can change CAN protocol clock speeds on-the-fly to the correct speed. CAN FD BRS is sensitive to the protocol clock speed, so its nice to be able to change just that clock domain. Especially for high speed CPUs, you might want your peripherals clocked off a lower speed PLL so the ratio is exact and maybe reduce PLL power/noise/etc.