Nitpick, but the PIC32MX MCUs use the M4K core.
Alright. I assumed the M4K was considered a part of the microAptiv line, apparently not. It doesn't change the reasoning though, and I believe the architectures are close enough.
but I do remember the STM32F101 topping out at 36MHz. By 2009 there were definitely Cortex-M3 devices going up to 100MHz on the market.
Yes, but not in 2007 when the PIC32MX was released. I mentioned the NXP LPC1700 line which was released in 2008, Cortex-M3 and going up to 100 MHz. Still one year later and as I mentioned, on a much costlier process node.
Maybe it's a much more clumsy architecture but I'd be interested in getting facts and details on that.
You can write quite complex firmwares for Cortex-M devices without requiring any assembly or compiler intrinsics. The PIC32Ms require quite a lot of compiler support to hide the ugliness. The whole KSEG/USEG split, and especially the KSEG0/KSEG1 aliasing, adds a lot of complexity if you want to customize the memory layout. The MIPS architecture also carries a lot of baggage, eg. every PIC32M starting up in single-vector interrupt mode because that's how ancient MIPS processors worked, and it's somehow important to be compatible with that.
I get the point, but whether those are issues is up for debate.
I'm certainly no specialist of the MIPS architectures, but the split between a "kernel space" and "user space" bears some security advantages despite being somewhat more difficult to handle. Granted, it looks like a somewhat "ancient" way of segmenting memory but it's not necessarily bad per se.
The Cortex-M3 and M4 have optional MPUs and a lot of MCUs have been released without one AFAIK.