I've been working on an AVR programmer using a m328p clocked at 16Mhz. The datasheet for the 13a says the same thing as the other tiny AVRs:
The minimum low and high periods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
The 13s have the CLKDIV8 fuse set (lfuse: 0x6A), so they should be OK with a 300kHz clock (9.6Mhz/8 /4). Testing with a USBASP at 187500 works OK, and 375kHz fails as expected.
Using the m328p clocked at 16Mhz, I used SPI DIV64, for a 250kHz clock, but it didn't work. DIV128 (125kHz) worked OK. I wondered if I had messed up the SPI clock settings, so I put a scope on the SCK line and confirmed DIV64 gives 250kHz and DIV128 gives 125kHz.
I tried this with 3 different attiny13a-pu, date code 1430, and got the same result. Any ideas what's going on? Datasheet errata (i.e. 3 clock cycles are required for fck >9 Mhz) ? Batch of chips out of spec?
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