Can't output on PIC18F4420 RA7

[Opti]

Been bashing my head against this for a few days now  and I've exhausted everything I can come up with. I've got a couple PIC18F4420s that I'd like to use in a project I'm working on, but I need all the IO I can come up with which means using the internal oscillator to free up RA6/RA7. The problem is, even with my simplest code, I can't get RA7 to work.

Code: [Select]

// PIC18F4420 Configuration Bit Settings

// 'C' source line config statements

// CONFIG1H
#pragma config OSC = INTIO67    // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOREN = SBORDIS  // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 3         // Brown Out Reset Voltage bits (Minimum setting)

// CONFIG2H
#pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC   // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = ON      // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
#pragma config LPT1OSC = OFF    // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#include <xc.h>

#define _XTAL_FREQ  8000000

void main(void) {
    OSCCON = 0x72;
   
    TRISAbits.TRISA5 = 0;
    TRISAbits.TRISA6 = 0;
    TRISAbits.TRISA7 = 0;
   
    LATAbits.LATA5 = 0;
    LATAbits.LATA6 = 0;
    LATAbits.LATA7 = 0;

    while(1) {
        LATAbits.LATA5 = !LATAbits.LATA5;
        LATAbits.LATA6 = !LATAbits.LATA6;
        LATAbits.LATA7 = !LATAbits.LATA7;
        __delay_ms(1000);
    }
   
}

From the above, RA5 works as expected. RA6 works as well, indicating (I think) that the configuration bits are set correctly as the only other internal oscillator mode has RA6 become CLKO clock out. However, RA7 does nothing, no output. If there is any voltage on the line, it will float. Initializing the latch to 1 doesn't produce an output. Trying a second PIC18F4420 produces the same results, so I don't think I'm working with a cooked chip/pin and feel like I'm missing something obvious, but I've been staring at the datasheet and forum searches for too long now. 

Only other thing I can think of - I'm programming using a TL866II+ instead of a PICkit, but that's all I can come up with that's unusual.

Appreciate any help steering me in the right direction!

[MarkF]

I have a different setup for OSCCON using a pic18f4620 running at 32MHz internal clock
Note:  OSCCON must be set BEFORE OSCTUNE in order to have the PLL work correctly

Code: [Select]

   OSCCON=0x70;               // Select primary oscillator @ 8MHz
   OSCTUNE=0x40;              // Select 4 x PLL for INTOSC

But, you are not using the PLL.  So, I don't get it.
Try forcing the bits instead of relying on read-modify-write:

Code: [Select]

   while(1) {
      LATA = 0xff;
      __delay_ms(1000);
      LATA = 0x00;
      __delay_ms(1000);
   }


[SuzyC]

CONFIG1   FOSC0:3 

Set FOSC to:

  0x1000 = Internal oscillator block, port function on RA6 and RA7

[Dabbot]

That's what it's set to according to the code.

From 18f4420.cfgdata:
CVALUE:8:INTIO67:Internal oscillator block, port function on RA6 and RA7

[Opti]

I have a different setup for OSCCON using a pic18f4620 running at 32MHz internal clock
Note:  OSCCON must be set BEFORE OSCTUNE in order to have the PLL work correctly

Code: [Select]

   OSCCON=0x70;               // Select primary oscillator @ 8MHz
   OSCTUNE=0x40;              // Select 4 x PLL for INTOSC

But, you are not using the PLL.  So, I don't get it.
Try forcing the bits instead of relying on read-modify-write:

Code: [Select]

   while(1) {
      LATA = 0xff;
      __delay_ms(1000);
      LATA = 0x00;
      __delay_ms(1000);
   }


So this wasn't the answer, but it set me on the right path. Looking at your OSCCON settings, I went back and re-evaluated why I had 0x72 set, and it was because if I set 0x70, things wouldn't work for me, and that bad behavior made me realize that it just plain didn't seem like the configuration settings were getting to the chip. Long story short, the programming software I was using from Linux clearly wasn't doing the job correctly, as soon as I programmed the chip from the Windows software everything worked fine.    Frustrating, but at least it's fixed now and I can actually move forward with my project!

Thanks to you and the others in the thread for help!