Open (functional!) core for Ethernet / VHDL for Ethernet - Spartan 6?

[Kremmen]

My choice of FPGA is already included in the topic. It would be too heavy to change toolchains at this stage so a Spartan it has to be. Also i already made the decision to use the MCU for Ethernet because there is no compelling reason to use the FPGA and it appears to be an order of magnitude harder to do it there without spendig a lot of cash on licensed IP.
I am now in the process of designing the MCU-FPGA interface based on external bus connection, so any brilliant ideas there are welcome. The MCU is Atmel AT32UC3C due to the simple fact that i have a complete functional toolchain for it, at it should manage the requirements handily.

[gxti]

The milkymist project has a 100mbit mac that works on Spartan 6. It's also used in the OpenRISC SOC project (orpsoc), which I successfully ran on a Digilent Atlys. Would have been flawless if not for a software issue -- the kernel driver did not instruct the PHY to negotiate at 100mbit and it negotiated gigabit by default, which of course doesn't work on a 100mbit mac. For lack of skill I just configured the switch to force 100mbit and everything was great.

As for how hard it will be to interface with the MAC without a CPU, I can't really help you there. Should be easier than talking directly to a PHY, I would hope.

[Kremmen]

You need to compare the implementation complexity of the FPGA based solution with the complexity of the same thing done in an MCU. The UC3 chip i have selected has a regular MII interface to a PHY, in this case either Micrel or TI device. The MCU implements the MAC in hardware and microcode of whatever you want to call that part. What remains is to insert the rest of the stack and that i will do using LwIP. It even seems to be part of the Atmel SW framework.
LwIP offers the functionality i need, i.e. reliable transport on the TCP level, using an easy call interface.
Based on my search and this thread, FPGAs don't come close to offering the same level in anything that is free or open.

[nctnico]

@Kremmen: A quick question did you ever use uIP? If yes, how does that compare to lwIP? I have used uIP but I did had to fix several bugs.

[Kremmen]

Sorry, no I never have. Also, as to LwIP i have used it for relatively basic TCP/IP things as far as networking goes, because my main interest is not the networking part. I only need that for high throughput data streaming between a master and slave devices in motion control systems. So i have only exercised a small subset of the whole functionality of the implementation.

[webphyfpga]

You can download a free demo of the WebPHY DATABUS IP Core from here:
http://www.webphyfpga.com

The IP core can send and receive data between a FPGA and web client over Ethernet using its web-based "rd" and "wr" commands.  The core also has a user-customizable web page allowing browser-based control of the FPGA.  The core connects to Ethernet via standard LVDS-configured IOBs on the FPGA.  No external PHY or DDR/Flash memory chips, software TCP stack or embedded CPU are required - everything is contained within the core.

[Kremmen]

Thanks for the info. While the website looks interesting it appears to target somewhat different use cases from mine. Anyway, that project is already done and the net part works under a MCU. But maybe for another project on another day...

[legacy]

i am thinking about buying a C8900 (Cirrus Logic) Ethernet board from Olimex (parallel interface), see their Ethernet modules, they also have ENC (SPI interface) by Microchip.

[Scrts]

Is there anything on OpenCores you could use?
http://opencores.org/projects

The 10/100 MAC for Altera Avalon bus from OpenCores is proven to work. I think it's even in Altera Wiki page.