I'm actually really interested in the PIO state machine, especially if you're emulating data protocols with timers, SPI, DMA, etc. just to make a differential Manchester go pretty over an AC coupled data line. It's all a mess. Having some if-this-then-that capability running inside the peripheral without CPU intervention could be very interesting.
I wouldn't expect this micro to be a bigseller. No onboard flash sounds like a hassle. But it could be an educational tool, as having 2 cores is not "(as) easy to program", and these experimental I/O features may be very useful to see in other microcontrollers.
Considering the FLASH/SRAM situation I would look at it this way: you can get a STM32L431 with 64kB RAM. With a few lines of linker & assembly code you can segment the SRAM into 16kB of data and 48kB of code, and save 1/3 power (energy). Depending on what you're doing, 48kB of code is still plenty for low power IoT stuff.
With 264kB of SRAM you could provision 64kB code for each core and have a shared 136kB for data. Or do 128K/64K code + 64K data. Optionally you can still run large libraries from FLASH. etc. That still sounds like plenty of memory for such a small and relatively slow core. It's not like this MCU has on-chip peripherals for Ethernet, camera, USB2.0HS, high resolution LCD controllers etc. that can easily chew up all the memory for assets.
I will probably order one too whenever I get around to it.
"daul core cortex M0+"
why?
why?
WHY?
also HOW?
I agree, the M0+core is optimised for low cost and low power, so shoving two of them into a micro instead of one of the more powerful variants (e.g. M33) doesn't make a lot of sense. I guess it's possible they intended to have one core running something like a TCP stack to remove the complexity/overhead from a users program running in the other one.
The lack of semi-decent analog peripherals is a major omission if they are targeting this to an educational or hobby market.
I think we take great ADC's/DAC's/comparators/opamps for granted from large MCU vendors. I was looking to use the ESP32 ADC lately and I was shocked what I saw. I was almost contemplating just putting an external I2C or SPI ADC just so I don't have to crunch my brain over calibration data, non-FS ranges and large sampling capacitor values.
Still this part is amazingly popular. Of course for it's WiFi/BLE capability.. but still.
I think it goes to show that designing digital systems can be facilitated/prepared very well with modern & free (as in free beer) FPGA tools. Yet analog is still much of a craft that requires a lot of knowledge to get right.