vhdl, could i adapt this dummy WB dram interface to a bram ?

[legacy]

Code: [Select]

-- Including libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Including dependencies
library work;
use work.softcore_pkg.all;

entity wb_sram is
port
(
clk : in std_logic;
reset : in std_logic;
interrupt : out std_logic;
slave_in : in  wb_master_out;
slave_out : out wb_master_in;

-- onboard SRAM1 (ISSI 256Kx16 SRAM, 10ns)
ad : out std_logic_vector (17 downto 0); -- address bus (18 Bit)
we_n : out std_logic; -- write enable
oe_n : out std_logic; -- output enable
dio_a : inout std_logic_vector (15 downto 0); -- data bus (16 Bit)
ce_a_n : out std_logic; -- chip enable
ub_a_n : out std_logic; -- upper byte enable
lb_a_n : out std_logic  -- lower byte enable
);
end wb_sram;


architecture behave_wb_sram of wb_sram is
   constant ADDR_W: integer:=18;
   constant DATA_W: integer:=16;

   signal addr : std_logic_vector (ADDR_W - 1 downto 0);

   signal data_f2s: std_logic_vector (DATA_W - 1 downto 0);
   signal data_s2f: std_logic_vector (DATA_W - 1 downto 0);
   signal mem : std_logic;
   signal rw : std_logic;
   signal data_reg: std_logic_vector (DATA_W - 1 downto 0);

begin
-- Interrupt not used, tie it to 0
interrupt <= '0';

-- The slave acknowledge is set by the cyc signal
slave_out.ack <= slave_in.cyc;

-- The slave data to be sent via the wishbone bus to the CPU are set with the read SRAM data
-- Because the data width of the SRAM is only 16 bit the other 16 bit are tied to 0
slave_out.data (31 downto DATA_W) <= (others => '0');
end behave_wb_sram;


hi guys
the code is about a dummy WB interface to a RAM controller which interface the soft core to a DDR ram of 256Kword. I'd like to implement this soft core on Spartan s3e 500 breakout board which has no dram, i'd like to use the BRAM (which is included inside the fpga), and i have resources enough to have 32Kbyte of BRAM available.

The question is: can i adapt this WB interface to interface bram instead ? I aim for minimal impact to the vhdl code of the SoC.

[nctnico]

I think this is relatively easy to do. There is a package to create a dual port wishbone memory from blockrams. That should be a drop-in replacement.

[legacy]

perfect, thank you =)