What I'm trying to do: Use a Nexys4 DDR board (Xilinx Artix-7 FPGA XC7A100T-1CSG324C) to capture analog signals, do some processing on them, and output the resulting data over USB. The dev board has an FTDI FT2232 onboard, wired for two-wire serial communication. The FPGA has a built-in ADC module, which Xilinx calls XADC. I'm using VHDL because I have somewhat more experience with that than with Verilog. This is part of a project for school, so using a language my advisor / instructor knows well seemed like a good idea.
At this stage, all I want to do is take data from the XADC and send it out the serial port.
I'm not sure how to simulate this thing properly. The ADC never seems to do anything, so the UART never gets started. This has made debugging the issue difficult.
The code I'm using for the UART is mostly hamster_nz's example code with comments added and style changes to make things easier for me to understand.
Xilinx's XADC documentation isn't entirely clear to me. I think drdy_out indicates that data is ready, and do_out contains the data word output. Since I'm running the ADC in continuous conversion mode with the channel sequencer and 4 channels enabled, the documentation seems to indicate that it should cycle through the channels, output data when each conversion finishes, and indicate which channel it came from on channel_out. I don't think I should need to manually change channels by writing the channel address to daddr_in, but I'm not sure on this.
Can anyone help? This seems like it should be simple, but Xilinx are masters at making the simple complicated, and I'm apparently amazing at overthinking things and going in circles...
I've attached a file with just the sources and not the generated mess Vivado spews out.