New wireless module announced with RISCV & USB interface

[mon2]

By Sipeed:

https://twitter.com/SipeedIO/status/1608366512083193857

New Tiny #tinyML #AIoT module M0S coming out~
Based on BL616, WiFi6+BT5.2+Zigbee, 384MHz #RISCV RV32GCP, 4MB Flash + 512KB SRAM, and USB2.0 HS in tiny 10x11mm stamp module!
It would be <2$ ~

[ataradov]

Just another completely undocumented chip. The USB chapter of the RM is literally empty. Not a single word.

[martinribelotta]

Just another completely undocumented chip. The USB chapter of the RM is literally empty. Not a single word.

But is completelly documented: https://dl.sipeed.com/shareURL/Maix-Zero/M0P/6_Chip_Manual

More than other chinese chips... sure... is not a NXP datasheet with varios MBy of application notes but have the essential information into this...

Aditionally, boufallo have a very open repository:
https://github.com/bouffalolab/bl_mcu_sdk/tree/master/drivers/soc/bl616/std

[ataradov]

But is completelly documented:

Name one USB register based on this documentation.

[martinribelotta]

But is completelly documented:

Name one USB register based on this documentation.

Touche! Trully... the usb device lacks documentation completelly but the abailability of code:
https://github.com/bouffalolab/bl_mcu_sdk/blob/master/drivers/lhal/include/hardware/usb_v1_reg.h
https://github.com/bouffalolab/bl_mcu_sdk/blob/master/drivers/lhal/include/hardware/usb_v2_reg.h

(and correspondign sources) mitigate this lack... normally the usb core is a canned IPCore from synopsis or similar provider...

Lamentably, is an increasing practice in varios vendors like ST or NXP (and long date known from TI)

[hans]

Probably, I googled some register names and found this PDF: https://caxapa.ru/thumbs/655229/GM8136S_GM8135S_Data_Sheet_V0.2.pdf

See chapter 12.4. The in-depth explanation is sparse or non-existent. It does list the RTL in a slightly easier to read format than just C defines. It's clearly an IP core of some sort.. hoped to find which IP it is, because maybe that can point to more in-depth docs from the manufacturer (or to some Linux kernel driver if really desperate).

The v1 RTL seems fairly simple to operate, e.g. PIC16 USB levels of complexity.

[martinribelotta]

Probably, I googled some register names and found this PDF: https://caxapa.ru/thumbs/655229/GM8136S_GM8135S_Data_Sheet_V0.2.pdf

See chapter 12.4. The in-depth explanation is sparse or non-existent. It does list the RTL in a slightly easier to read format than just C defines. It's clearly an IP core of some sort.. hoped to find which IP it is, because maybe that can point to more in-depth docs from the manufacturer (or to some Linux kernel driver if really desperate).

The v1 RTL seems fairly simple to operate, e.g. PIC16 USB levels of complexity.

In my experience working with rtl-sw designs, normally the datasheet is internally and make references to testbenchs (normally in systemverilog)

Its not surprising that many small vendors take this approach:
 - Create IPCore or buy to another vendor like synopsis
 - test in SV some functionalities and run syntathic tests with very common use cases
 - use this synthetic tests as a template to generate a C HAL with minimal functionality

Yeeeeees, this is baaaad... but the time-to-market is incredible low and, from the point of sellers, have a minimal inversion on I+D

Many engieers (including me) prefer the old way with a big datasheet or (even better) a separate IPCore datasheet but is extremelly rare even for a big sellers like NXP or ST

The best way to do this thinks will be separate chip datasheet from IPCore datasheet and reuse both in many designs... this is far from reality

[mon2]

From the semiconductor's tech support group on the BL616:

Brief info: USB 2.0 High Speed, Host/Device mode.
We have release datasheet/user manual on github. Also please check with MCU SDK. I think you can find more details in USB stack code.
Yafei