Probably, I googled some register names and found this PDF: https://caxapa.ru/thumbs/655229/GM8136S_GM8135S_Data_Sheet_V0.2.pdf
See chapter 12.4. The in-depth explanation is sparse or non-existent. It does list the RTL in a slightly easier to read format than just C defines. It's clearly an IP core of some sort.. hoped to find which IP it is, because maybe that can point to more in-depth docs from the manufacturer (or to some Linux kernel driver if really desperate).
The v1 RTL seems fairly simple to operate, e.g. PIC16 USB levels of complexity.
In my experience working with rtl-sw designs, normally the datasheet is internally and make references to testbenchs (normally in systemverilog)
Its not surprising that many small vendors take this approach:
- Create IPCore or buy to another vendor like synopsis
- test in SV some functionalities and run syntathic tests with very common use cases
- use this synthetic tests as a template to generate a C HAL with minimal functionality
Yeeeeees, this is baaaad... but the time-to-market is incredible low and, from the point of sellers, have a minimal inversion on I+D
Many engieers (including me) prefer the old way with a big datasheet or (even better) a separate IPCore datasheet but is extremelly rare even for a big sellers like NXP or ST
The best way to do this thinks will be separate chip datasheet from IPCore datasheet and reuse both in many designs... this is far from reality