I have some decent amount experience in working with C/C++, Fortran and Python. I could give it a try to program an FPGA. But, my only concern is the cost. I'm looking for a low-cost alternative that it robust enough to give these 4 pulses with minimal jitter and without any false triggering.
Did you look at the Raspberry pi pico ?
The PIO engine on that can give lower trigger jitter and delay, than a MCU interrupt design.
That’s much cheaper than a fpga, and has modest SW complexity.
Latency <100 ns, anything more than that would significantly increase the dead time of my device.
+/- 5-10 ns would be an acceptable accuracy for the intended application.
As I explained in one of my replies, the delay between first two pulse and the last two pulses has to be variable. Ideally, these delays could vary between the two sets of pulses 100ns to 100's microseconds.
The Pico PIO will have sampling granularity of appx 7ns, so that sets your response jitter.
There is a latency delay of InPin -> sampler -> state engine -> sampler -> OutPin which will be 2-4 clks + a few ns. Should be well under your 100ns - I'd guess 21-49ns ballpark, with 7ns jitter.
Subsequent Edge to edge timing will be low jitter, and you could adjust the PIO PLL to fine tune that, if 7ns steps are too coarse.
eg pick 100Mhz for 10ns ruler, 90.9 MHz for 11ns ruler and 111MHz for 9ns ruler etc
If sampled clock delay quantize is too large for you, you could move into the somewhat analog domain with a Monostables, or triggered VCO+counters or Delay lines (ADI have a series )