well, I have given a look to the architecture, and listened a few presentations
What I think: I don't like a lot of things in this architecture
First of all: the belt! It's a queue register which shifts on the right (consequentely it loses a slot) every clock edge. This belt has been designed to solve the "renaming registers" problem which ussually afflicts VLIW-like architectures. So, you have a lot of processing in parallel, no general purpose registers, and the belt is the only way to pass and get information to and from them.
So, when you have to issue an operation, say C = A OPP B, you have to rename A, B, C in term of belt positions.
This point varies at every clock edge, and you also need to have an optimal scheduling data flow to understand the correct order.
Therefore is definitively something you can't assemble by hand like we have always done with 6800 or 68000, you need a compiler, it's a must!
It's even worse than the pipelined version of MIPS without the automatic stall and hazard unit, I mean where you have to manually consider every dependency between stages and registers and manually reschedule in the correct order, or fill a NOP between operations as well as you have to do with in order to solve the "delayed slot" which always happen on a branch.
Well, there are RISC-architectures (like 88K) where the hardware can automatically fill a NOP after the branch, you just need to set the proper bit, and forget about it.
RISC like MIPS are hard to be programmed in assembly. PowerPC is more friendly but even more complex, ARM is the most friendly in the family.
Btw all of those are still programmable in assembly, whereas Mills is definitively a no-go since it's virtually impossible for a human being.
The belt-solution looks horrible for me