I solved the problem differently. This method should work for almost any board, not just AVNET.
First, download the AVNET board-definition files from
http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm You might need to register on the site and then search for XBD (i.e. Xilinx Board Definition) files for your board. I have included a ZIP file for AVNET's Spartan-6 LX9. Extract the files to the board directory (e.g. C:\Xilinx\13.4\ISE_DS\EDK\board\Avnet\), so that you have two subdirectories \boards and \ipxact containing the unzipped files.
Then, start up Xilinx's Project Navigator, create a project, select YOUR AVNET board that should now show. Then go to Project...New Source...Embedded Processor. Type in the name of the embedded processor, e.g. mb_system. Soon after Xilinx Platform Studio opens up (and likely complains about license. Ignore it. Answer "yes" to "....Do you want to create a base system using the BSB wizard?"
Then select "PLB..." radio button, and then you'll be guided though "Welcome", "Board" is AVNET Spartan-6 LX9 is preselected (or the one you chose earlier). Press "Next", "Next" until you get to "Peripherals".
Highlight all the peripherals on the left-side and click "Add". This will guarantee that all peripherals on the AVNET board will have definitions in the board UCF you are creating. Then click "Next". XPS creates the board definition files alongside all its other outputs, displays a summary of the system resources you are using. Click "Finish" and close XPS.
Go back to Project Navigator, then "Project...Add Source ..." and navigate to the folder with the name above e.g. "C:\Xilinx\Embedded\tutorial_02\mb_system\data" in my case. You will find "mb_system.ucf". That is the file you need. Add it to the project and once it is loaded, double click on it to view its contents. It should look something like this:
# Avnet Spartan-6 LX9 MicroBoard
Net fpga_0_USB_UART_RX_pin LOC=R7 | IOSTANDARD = LVCMOS33;
Net fpga_0_USB_UART_TX_pin LOC=T7 | IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_4Bits_GPIO_IO_O_pin<0> LOC=P4 | IOSTANDARD = LVCMOS18;
Net fpga_0_LEDs_4Bits_GPIO_IO_O_pin<1> LOC=L6 | IOSTANDARD = LVCMOS18;
Net fpga_0_LEDs_4Bits_GPIO_IO_O_pin<2> LOC=F5 | IOSTANDARD = LVCMOS18;
Net fpga_0_LEDs_4Bits_GPIO_IO_O_pin<3> LOC=C2 | IOSTANDARD = LVCMOS18;
Net fpga_0_DIP_Switch_4Bits_GPIO_IO_I_pin<0> LOC=B3 | IOSTANDARD = LVCMOS33 | PULLDOWN;
Net fpga_0_DIP_Switch_4Bits_GPIO_IO_I_pin<1> LOC=A3 | IOSTANDARD = LVCMOS33 | PULLDOWN;
Net fpga_0_DIP_Switch_4Bits_GPIO_IO_I_pin<2> LOC=B4 | IOSTANDARD = LVCMOS33 | PULLDOWN;
Net fpga_0_DIP_Switch_4Bits_GPIO_IO_I_pin<3> LOC=A4 | IOSTANDARD = LVCMOS33 | PULLDOWN;
Net fpga_0_SPI_FLASH_SCK_pin LOC=R15 | IOSTANDARD = LVCMOS33;
Net fpga_0_SPI_FLASH_MISO_pin LOC=R13 | IOSTANDARD = LVCMOS33;
Net fpga_0_SPI_FLASH_MOSI_pin LOC=T13 | IOSTANDARD = LVCMOS33;
Net fpga_0_SPI_FLASH_SS_pin LOC=V3 | IOSTANDARD = LVCMOS33;
Net fpga_0_SPI_FLASH_SPI_HOLDn_pin LOC=V14 | IOSTANDARD = LVCMOS33;
Net fpga_0_SPI_FLASH_SPI_Wn_pin LOC=T14 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC = H17 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC = L15 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC = N17 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC = P17 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC = T17 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC = N16 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC = N15 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC = P18 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC = M18 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC = N18 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC = T18 | IOSTANDARD = LVCMOS33 | TIG;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC = L17 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC = K18 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC = K17 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC = J18 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC = J16 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_MDC_pin LOC = M16 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_MDIO_pin LOC = L18 | IOSTANDARD = LVCMOS33;
Net fpga_0_CDCE913_I2C_Sda_pin LOC=U13 | IOSTANDARD = LVCMOS33 | PULLUP;
Net fpga_0_CDCE913_I2C_Scl_pin LOC=P12 | IOSTANDARD = LVCMOS33 | PULLUP;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 66666.7 kHz;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin | LOC=K15 | IOSTANDARD = LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC=V4 | IOSTANDARD = LVCMOS33 | PULLDOWN;
###### microblaze_0
### Set Vccaux for S6LX9 MicroBoard to 3.3V ###
CONFIG VCCAUX = "3.3" ;
###### Ethernet_MAC
### Pull-ups on RXD are necessary to set the PHY AD to 11110b. ###
### Must keep the PHY from defaulting to PHY AD = 00000b ###
### because this is Isolate Mode ###
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> PULLUP;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> PULLUP;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> PULLUP;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> PULLUP;
---------------------------
Scream YEY! if this helped.