Want to know WCET for an SPI ISR dsPIC33FJ12MC201

[perdrix]

I've written an SPI ISR for a dsPIC33FJ12MC201.   I would like to know how to determine the Worst Case Execution Time (WCET) for that code (or at least a reasonable approximation) .  I'm using the free version of MPLAB.   Nested interrupts are not allowed.

The clock code setup is:

Code: [Select]

#ifdef XTAL
#pragma config FNOSC = PRIPLL       // Primary Oscillator (XT, HS, EC) w/ PL
#pragma config POSCMD = XT          // XT Oscillator Mode
#pragma config IOL1WAY = OFF        // Allow Multiple Re-configurations
#else
#pragma config FNOSC = FRCPLL       // Internal Fast RC (FRC) w/ PLL
#pragma config POSCMD = NONE        // Primary Oscillator Disabled
#pragma config IOL1WAY = OFF        // Allow Multiple Re-configurations
#endif

void init_clock(void) {
#ifdef XTAL
    SetPreDiv(5); // 10MHz / 5 = 2MHz
    SetPLLdiv(72); // 2MHz * 72 = 144MHz
    SetPostDiv(2); // 144MHz / 2 = 72MHz
#else
    //
    // 7.372800 MHz + 25 steps of 0.375% = 8.064000MHz
    //
    SetOscTun(25); // 9216 * (800 + 3 * 25) = 8064000
    SetPreDiv(7); // 8064KHz / 7 = 1152KHz
    SetPLLdiv(125); // 1152KHz * 125 = 144MHz
    SetPostDiv(2); // 144MHz / 2 = 72MHz
#endif
}

The internal oscillator is being used, not an external XTAL.   I *think* the comments in initclk() are correct, if not please could you put me straight.


Thank you, David

[DavidAlfa]

Read DS70000600D
Interrupt latency is decribed in page 16. Better you read it whole to better understand how it works.

MPLAB is always free. It's the compilers which have PRO version.
Most microchip compilers let you use O2 optimizaton for free, no restrictions. which is already a pretty nice optimization level.

You can use MPLAB SIM, setting breakpoints at the start and end of the ISR, check the core cycle counter, and use it to calculate the execution time.
After reading DS70000600D you'll know the ISR delay is 13 cycles, so add them to the counter value.