Looking to use a CPLD. Which one to go for...?

[legacy]

I have the same need for CPLD I need to attach to a 5V bus. I am going to use an old XC95108 CPLD, which comes with 3.3V or 5V I/O capability.

the data sheet says

• VCC, Supply voltage relative to GND, up to7.0V
• VIN, Input voltage relative to GND, up to VCC + 0.5V
• VTS, Voltage applied to 3-state output, up to VCC + 0.5V
• VCCINT, Supply voltage for internal logic and input buffers, up to 5.25V
• VCCIO
  
  • Supply voltage for output drivers for 5V operation, up to 5.5V
  • Supply voltage for output drivers for 3.3V operation, up to 3.6V

which sounds that I can put VCC=VIN=VTS=VCCINT=VCCIO=VCC_BUS=5V, right ?

[legacy]

ZX Breakout 

interesting 

[uncle_bob]

That arrow page says no stock. Was there an alternative supplier.
I only ever looked at de-nano boardsbefore.

Hi

Yup, the cheap Bemicro boards are currently not in stock. They are (as far as I know) a sole source thing from Arrow. Some of their expensive are very similar to or are the same as the Terasic boards. Those show up as De Nano's of various sorts. Some of them are better than others. There are a lot of sources for Terasic boards.

Bob

[legacy]

here I have an old Atlera flex10K fpga board, it comes with its flash programming chip and its byte blaster interface (parallel port)
it requires QuartusII v5 (I have a copy, webpack=free license) as its support has gone dropped

I think I will put it on ebay as I prefer to use a XILINX XC95xx CPLD

[uncle_bob]

Before you decide which one it will be, make sure the version of the IDE you need for the part is supported by the OS you're running.

Example: I had a Altera Cyclone II board, that only is supported by an older version of the IDE (13.x) and that version only runs on Windows 7 - and I'm on 8 and 10. I have tried it anyway and indeed it did not work (why? I did not put time into that to find out).

[2c]

Hi

The Quartus guys moved over to a "64 bit only" approach back around version 12 or so. Their stuff all runs on anything from Win 7 on forward as long as it is 64 bit. Some of their newer versions run on things other than Windows as well.

Bob

[legacy]

I wonder if it is possible to raise the CPLD's ground reference to shift up its logic levels...

Been there, done that. Not a real good idea. You get into all sorts of nasty diode clamp issues. Outputs swing sort of right until you hit a tri-state port. Inputs clamp on both sides, with occasional "interesting" outcomes. (as in you source enough current into the part to take the top or bottom side rail to +5 or to ground).

I do not understand the point, as the XC95108 data sheet says that
you can provide 5V to the internal logic and input buffers (VCCINT)
and 5V to the output drivers (VCCIO) 

exactly, what have you done, guys ? and which is the nasty diode clamp issue ?

[legacy]

Interfacing 3V and 5V applications: found a good Application Note by nxp 
 

[uncle_bob]

I wonder if it is possible to raise the CPLD's ground reference to shift up its logic levels...

Been there, done that. Not a real good idea. You get into all sorts of nasty diode clamp issues. Outputs swing sort of right until you hit a tri-state port. Inputs clamp on both sides, with occasional "interesting" outcomes. (as in you source enough current into the part to take the top or bottom side rail to +5 or to ground).

I do not understand the point, as the XC95108 data sheet says that
you can provide 5V to the internal logic and input buffers (VCCINT)
and 5V to the output drivers (VCCIO) 

exactly, what have you done, guys ? and which is the nasty diode clamp issue ?

Hi

If you take a part that does not have 5V outputs (or inputs) and:

       Raise the ground pin on the part up to 0.9V

      Feed the supply with 4.2V

You have a part that swings roughly equally to both sides of 2.5V. Most 5V CMOS data sheets suggest that the logic threshold is at 2.5V plus minus some tolerance. (it isn't, but that's not part of this story). The 3.3V part has a 3.3V supply. If you run up to 3.6V, it's pretty much the same with slightly different numbers.

Normally the low side is done with some sort of series drop element (like a pair of low barrier voltage diodes). The high side is done with an adjustable series regulator. It all looks fine on paper.

Now, pull all the inputs low. The clamp diodes all fire and the low side voltage goes below your 0.9V supply. Worse yet, pull an output low. Then the 0.9V goes right to ground if it's pulled hard enough. (pull down resistor or something else).

Next pull all the inputs high. Again the clamp diodes all fire and your part is running off of the +5 through the clamp diodes rather than your series 4.3V regulator. Same issue if an output gets pulled high.

If you started with 3.3V you may or may not have fried the chip yet.

Now take some of the lines high and some of them low. You have both effects at the same time. Likely your supply is over the max on the chip at this point.

All of this is just looking at the output transistors and input clamps. It does not include neat stuff like parasitic stuff that gets triggered when you are above supply or below ground. Since you can get in trouble just with the outputs, having a part with no clamp to the high side rail does not keep you out of trouble. In the context of "drop it into anything" the split supply thing is not a good idea.

Bob

[Bruce Abbott]

I do not understand the point, as the XC95108 data sheet says that you can provide 5V to the internal logic and input buffers (VCCINT) and 5V to the output drivers (VCCIO)

The point is that the XC95108 is discontinued and unobtainable. Some 9500XL series parts are still available, but they are 3.3V Vccio only.

The 'nasty clamp diode issue' doesn't apply to 9500XL because they don't have clamp diodes, but you might have trouble driving 3.3V logic high into a line that is pulled up to 5V. Pullups are usually only used with open collector drivers, in which case it isn't a problem. However a dodgy circuit might use pullups to raise the voltage when interfacing between TTL and CMOS.   

All this means is that - as always - you should determine the specific requirements of the device you are interfacing to before deciding which chips to use.
 

[Tronix]

Thanks for all the replies. Just read through it all.

but you might have trouble driving 3.3V logic high into a line that is pulled up to 5V.

I would have that problem with some of the signal lines.

[Bruce Abbott]

I would have that problem with some of the signal lines.

What are you interfacing to, and which signals lines in it have pullups?

[legacy]

the real problem I have: 32bit on the data bus line, plus 24 bit on the address bus line, plus 4 bit on the control bus line
all of these at 5V, while I have to use a Spartan6 fpga, which is 3.3V:  I will need to put a lot of level-shifter buffers in the middle
and the PCB will be bloated about that 

[legacy]

The point is that the XC95108 is discontinued and unobtainable. Some 9500XL series parts are still available, but they are 3.3V Vccio only.

recently, I have bought a few of them from ebay uk 

[Bruce Abbott]

the real problem I have: 32bit on the data bus line, plus 24 bit on the address bus line, plus 4 bit on the control bus line

What computer are you interfacing to, and what is the purpose of your device?

recently, I have bought a few of them from ebay

Lucky you!

[legacy]

What computer are you interfacing to, and what is the purpose of your device?

ah, it's a bus, a synchronous bus, made by Motorola in 1994, it needs a finite state machine in order to handle the access (eventually in burst mode)
the fpga should implement the fsm, plus a few extra devices, including a super fast serial, able to shoot up to 3Mbps (over usb), and a dram controller

I am not sure if to use the fpga's PLL (every good fpga has a built in one, I guess), or if I'd better an external PLL (e.g. MC88915? MC88916?): with "clock distribution in mind" engineers in Motorola have designed it to export half the clock frequency (12.5Mhz) over the connector (a big 96pin, 3 row of 32 pins), so I need to double it locally (25Mhz) in order to provide the right synchronization to the fsm.

[uncle_bob]

What computer are you interfacing to, and what is the purpose of your device?

ah, it's a bus, a synchronous bus, made by Motorola in 1994, it needs a finite state machine in order to handle the access (eventually in burst mode)
the fpga should implement the fsm, plus a few extra devices, including a super fast serial, able to shoot up to 3Mbps (over usb), and a dram controller

I am not sure if to use the fpga's PLL (every good fpga has a built in one, I guess), or if I'd better an external PLL (e.g. MC88915? MC88916?): with "clock distribution in mind" engineers in Motorola have designed it to export half the clock frequency (12.5Mhz) over the connector (a big 96pin, 3 row of 32 pins), so I need to double it locally (25Mhz) in order to provide the right synchronization to the fsm.

Hi

Most FPGA's have PLL's in them. This thread has mixed CPLD's and FPGA's without identifying which is which. CPLD's often do not have PLL's. If you have a FPGA and a PLL in it, your timing closure process (part of the design) will be much easier with an on chip PLL.

You can get parts that have a *lot* of buffers in one package. There is no need to buy them one buffer at a time. If I'm adding correctly, you have 32+24+4 = 60 lines. With hex inverters (a very low density approach) that's 10 packages. With octal transceivers, you are down to 8 packages. That's without getting into anything very crazy.

Bob

[legacy]

This thread has mixed CPLD's and FPGA's without identifying which is which

as already written:

• CPLD XC95108, PLCC, I/O @ 5V, already bought
• FPGA spartan6, I/O @ 3.3V + buffer level shifter, I have not decided which one in in s6e family

I had forgotten to specify: they are used in two different projects (CPLD-> glue logic for RAM-DISC, FPGA-> DRAM ctrl + fast uart)
even if, they are going to be used in the same board

[legacy]

If I'm adding correctly, you have 32+24+4 = 60 lines

yes, correct, but the bus is 5V, while s6e is 3.3V, unfortunately it's not 5V tolerant
so, I need external Dual-Supply buffers, in order to adapt the bus voltage (5V) to the fpga voltage (3.3V)


the CPLD project has no issue, the CPLD is already 5V and it's involved only as glue logic with a few lines from the bus
(5 signals in total: 3 input, 2 output), so, the PCB will be easy, in this case

project1 and project2, will be implemented in two different PCBs, as "expansion" cards.

[uncle_bob]

If I'm adding correctly, you have 32+24+4 = 60 lines

yes, correct, but the bus is 5V, while s6e is 3.3V, unfortunately it's not 5V tolerant
so, I need external Dual-Supply buffers, in order to adapt the bus voltage (5V) to the fpga voltage (3.3V)


the CPLD project has no issue, the CPLD is already 5V and it's involved only as glue logic with a few lines from the bus
(5 signals in total: 3 input, 2 output), so, the PCB will be easy, in this case

project1 and project2, will be implemented in two different PCBs, as "expansion" cards.

Hi

If you have 24 address lines - do you need to read them or only write to them? (or only read and not write). I'm guessing it is one or the other, but not both. Either way, a very standard single supply tri-state buffer with TTL level inputs should do the trick. If it's a drive the address thing, the power is +5 and 3.3V logic will toggle TTL levels fine. If it's read the lines, you do a 3.3V supply and let the 5V immunity of the chips do it's thing.

The 4 control lines may or may not fit in the same category as the address lines, same set of questions apply.

On the data lines, yes you need some sort of bidirectional gizmo. It will have to run on +5. If it has TTL thresholds, you are ok on the inputs. If not, do the very standard pull up level shift and drive them off of 3.3V. On the outputs, you know they are going from 0 to 5V. You need 0 to 3V .... a resistive divider does that quite well. At the very slow speeds you are talking about it all works pretty well. You have essentially zero gate loads to deal with on the dividers. Near zero C makes the RC time constant mighty small. (Ok some math, if the resistors are 1K and 2K, their parallel combo is 750 ohms. 750 times 10 pf gets you to 7.5 ns. Your 12.5 MHz clock has a period of 80 ns. There's no reason to be up as high as 1K or 10 pf ...

Bob

[Bruce Abbott]

I need external Dual-Supply buffers, in order to adapt the bus voltage (5V) to the fpga voltage (3.3V)

That fpga's not looking so wonderful now, is it?

The magic that high gate-count fpga's do comes at a price - the need to operate on very low voltage. Manufacturers don't build in 5V level converters because they are expensive, and the market for 5V compatible devices is too small.

So if you want to use your fpga on a 5V bus then you will just have to 'bite the bullet' and install external buffers. In the old days such buffering was standard practice (even on purely 5V systems) because the bus driving capability of CPUs and peripheral chips was often very limited.


   

[legacy]

• the address lines need to be input only, in this project I do not need DMA
• the data lines need to be bidirectional
• ctrl lines is composed by 3 inputs, and 2 outputs

[legacy]

So if you want to use your fpga on a 5V bus then you will just have to 'bite the bullet' and install external buffers. In the old days such buffering was standard practice (even on purely 5V systems) because the bus driving capability of CPUs and peripheral chips was often very limited.

yes, I come from the 80s, I remember when I had to add a lot of 245 and 244 chips and then the PCB became more complex 

in my case, I might go for Spartan2, it's 5V tolerant, already successfully used in my Nintendo ADV (it's a project I made in 2003), but nowadays … I have difficulties in finding these chips

while it's almost easy to find a few XC95108 chips on Ebay, even if they are a bit expensive (10-20-30 euro),  apparently there is a little demand of these CPLD I guess because of their legacy feature and because they do not require external SPI flash which makes them perfect for "glue logic" in order to replace damaged chips in 5V systems

contrariwise it's difficult to see spartan2e chips, it smells they have zero demand 

[nctnico]

There are version of the 245 and 244 which are easier to route (IIRC 545 and 544) and if you use the TSOP versions they are almost inline with the signals and take very little space.

[legacy]

244 and 245 like, but Dual-Supply buffers
so, I can supply one end at Vcc1=5V, and the other end at Vcc2=3.3V

[Bruce Abbott]

244 and 245 like, but Dual-Supply buffers
so, I can supply one end at Vcc1=5V, and the other end at Vcc2=3.3V

Yes. The 74LVX4245 is a TTL compatible dual supply equivalent of the 245. You can also use it replace a 244 by tying OE low and DIR high or low.

The 74HC4050 is useful if you just need a few extra inputs (6 buffers per package).