I only have the code for D21. It is essentially the same code, but APBxMASK is located in MCLK, not in PM. And clock enabling will look something like this:
GCLK->PCHCTRL[TCC0_GCLK_ID].reg = GCLK_PCHCTRL_GEN(0) | GCLK_PCHCTRL_CHEN;
while (0 == (GCLK->PCHCTRL[TCC0_GCLK_ID].reg & GCLK_PCHCTRL_CHEN));
Also, TCC has many modes. The code below is for simple PWM.
void APP_PwmInit(void)
{
HAL_GPIO_R_out();
HAL_GPIO_R_pmuxen(PORT_PMUX_PMUXE_F_Val);
HAL_GPIO_G_out();
HAL_GPIO_G_pmuxen(PORT_PMUX_PMUXE_F_Val);
HAL_GPIO_B_out();
HAL_GPIO_B_pmuxen(PORT_PMUX_PMUXE_F_Val);
HAL_GPIO_W_out();
HAL_GPIO_W_pmuxen(PORT_PMUX_PMUXE_F_Val);
PM->APBCMASK.reg |= PM_APBCMASK_TCC0;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(26/*TCC0_GCLK_ID & TCC1_GCLK_ID*/) |
GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(0);
TCC0->CTRLA.reg =
TCC_CTRLA_PRESCALER(TCC_CTRLA_PRESCALER_DIV1_Val) |
TCC_CTRLA_PRESCSYNC(TCC_CTRLA_PRESCSYNC_PRESC_Val);
TCC0->WAVE.reg = TCC_WAVE_WAVEGEN(TCC_WAVE_WAVEGEN_NPWM_Val);
TCC0->PER.reg = PWM_TOP;
TCC0->CTRLA.reg |= TCC_CTRLA_ENABLE;
}
static void pwmUpdatePwmChannels(void)
{
TCC0->CTRLA.reg &= ~TCC_CTRLA_ENABLE;
TCC0->COUNT.reg = 0;
TCC0->CC[0].reg = 111;
TCC0->CC[1].reg = 222;
TCC0->CC[2].reg = 333;
TCC0->CC[3].reg = 444;
TCC0->CTRLA.reg |= TCC_CTRLA_ENABLE;
}