I have a stm32g031 (nucleo32 board), which is not very different for LSE (I presume). It seems there is a DBP bit in PWR CR1 that has to be set to allow access to the RCC BDCR register after a reset. And of course to get at the PWR registers you need rcc again.
RCC->APBENR1 or_eq (1<<28); //PWREN, allows writing to PWR CR1
PWR->CR1 or_eq (1<<8); //DBP disable rtc domain write protection, allows writing to RCC BDCR
RCC->BDCR or_eq 1; //LSEON
while( (RCC->BDCR bitand 2) == 0 ){} //wait for LSERDY, should have a timeout
My stm32g031 has alternate functions listed for PC14/15, which I don't think the L4 has. In this case, PC15 had AF0/AF1 as OSC32_EN and OSC_EN, but have no idea what these are and the LSERDY is set without touching the gpio config so I assume LSEON just overrides gpio.
These registers are also involved in low power things ,resets, etc., and looks like it takes some reading to understand which bits survive resets and a bunch of other details.
edit- I guess I should add that I have no idea what the stm32 hal is doing, but one would think its doing the above things, so the above was probably not much help, but I guess you have some registers you can now check out to see what their values are.