Assuming that the 68010 is on the A side, and I has a EPM7032 there as a small 5V-only CPLD for glue logic, I know that address and control lines only go from A side to B side but how do I determine when to disable OE? As of the data bus what signal should be used to control direction? Can I just parallel the OE of the two sets of the bus or do I need separate OE's?
There's only one OE, and one DIR. They both are controlled from the A side. In sn74LVC16T245 there are two 8-channel circuits, both with their own OE and DIR. All these are controlled from the same side (which is side A on the pinouts). So, of course, you can parallel them.
So rounding up, I need three 74LVC16T245 and one 74LVC1T45:
* one 16T245 for the data bus,
* one and half 16T245 for the address bus,
* the remaining half for the control bus except BG,
* and the 1T45 are specifically for the BG line.
The DIR of the address/control buses would be tied to a fixed level since the signal travel only one way, and the DIR of the data bus derives from the R/W signal from the CPU. The OE of all three bus shifter chip are paralleled together and derived from the BG signal. The 1T45 has fixed direction and is always enabled.
CPU inputs are fed directly with 3.3V CMOS outputs counting on the fact that 3.3V CMOS output levels can be correctly understood by 5V TTL inputs.
Now the 68010 can sit in its own 5V island, and the rest of the system can be implemented using standard 3.3V LVCMOS components like IS62WV51216BLL-55TLI 16-bit 1MB SRAM, M29W160EB-75 16-bit 2MB NOR Flash and XC6SLX9-2PQG144A FPGA.