Alright. I assumed the M4K was considered a part of the microAptiv line, apparently not. It doesn't change the reasoning though, and I believe the architectures are close enough.
It's a newer release of the architecture (MIPS32r3 vs MIPS32r2) which adds the microMIPS instruction set. So fairly similar, but also significant additions.
I'm certainly no specialist of the MIPS architectures, but the split between a "kernel space" and "user space" bears some security advantages despite being somewhat more difficult to handle.
Not directly, as you still need some mechanism to actually map the address space into USEG. On PIC32s with fixed mapping translations you have Microchip's bus matrix controller, which isn't the greatest mechanism, and on others you have a TLB. In any case, adding virtual addresses to the mix certainly doesn't make things simpler.
On "grown-up" hardware, the fixed address space split also adds its own complications. Eg. OpenBSD dropped support for 32-bit MIPS not too long ago, because the limited address space didn't allow for effective address layout randomization.
The Cortex-M3 and M4 have optional MPUs and a lot of MCUs have been released without one AFAIK.
Yes, and the specification of the MPU makes it almost unusuable, since the section size and alignment restrictions are far too coarse for practical use. I think this may have been improved in the ARMv8-M specification, but don't know offhand for sure.