Author Topic: Interface FPGA and microcontroller  (Read 12617 times)

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Offline DiTBho

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Re: Interface FPGA and microcontroller
« Reply #25 on: May 10, 2022, 06:52:24 pm »
Implement a simple uart device, and use it. Up to 2Mbps can be achieved and it's enough for basic use.
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Offline josuah

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Re: Interface FPGA and microcontroller
« Reply #26 on: May 11, 2022, 03:52:22 am »
I was wondering how I would handle Wishbone ACKs with SPI: there may be any (hopefully short) number of STALL cycles before the Wishbone peripheral answers. It is not enough to insert dummy cycles like done for SPI: the delay is not guaranteed constant-time.

Let's try with UART with sampling for now! It UART will let the answer happen asynchronously (A in UART after all) "when it's ready": whenever the slave happen to answer.
 

Online SiliconWizard

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Re: Interface FPGA and microcontroller
« Reply #27 on: May 11, 2022, 05:22:39 pm »
Agreed.  SPI would be easiest.  Make the MCU the master and the FPGA the slave for the easiest configuration since you're more comfortable with MCUs.

If the MCU supports SPI slave (which most do these days) and the OP is not comfortable with FPGAs, I would actually suggest the opposite.
As others have pointed out, implementing SPI slave in the FPGA will require clock domain crossing and I wouldn't suggest that for a first project even to my worst enemy. ;D
 

Offline SpacedCowboy

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Re: Interface FPGA and microcontroller
« Reply #28 on: May 11, 2022, 05:56:09 pm »
There's a fairly simple treatment of SPI <-> ARM (ARM master and FPGA slave) at fpga4fun.com. Clock-crossing it may be, but it's not so terrible to understand what's going on when the code is explained as it's written...
 

Offline khach

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Re: Interface FPGA and microcontroller
« Reply #29 on: May 12, 2022, 10:45:41 am »
SPI to slow for my application. But QSPI probably get enough speed of communication. Any example of realization such QSPI slave in FPGA side?
 

Offline Bassman59

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Re: Interface FPGA and microcontroller
« Reply #30 on: May 12, 2022, 08:28:20 pm »
SPI to slow for my application. But QSPI probably get enough speed of communication. Any example of realization such QSPI slave in FPGA side?

It's pretty trivial to implement QSPI in an FPGA.

What gets interesting is if the QSPI in the FPGA has to interpret instructions sent on only one of the four lanes, or whatever other weirdness might be involved.
 

Offline Scrts

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Re: Interface FPGA and microcontroller
« Reply #31 on: May 12, 2022, 08:41:20 pm »
SPI to slow for my application. But QSPI probably get enough speed of communication. Any example of realization such QSPI slave in FPGA side?

SPI works well at 20Mbps. Do you really need more? If so, I'd opt for some parallel bus, like STM32 FSMC. If it's one way, you can also utilize camera interface.
 


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