I was wondering how I would handle Wishbone ACKs with SPI: there may be any (hopefully short) number of STALL cycles before the Wishbone peripheral answers. It is not enough to insert dummy cycles like done for SPI: the delay is not guaranteed constant-time.
Let's try with UART with sampling for now! It UART will let the answer happen asynchronously (A in UART after all) "when it's ready": whenever the slave happen to answer.