Don't bother with simulations because once you start doing more complex designs it will be unusably slow and you will have to un-learn relying on it
I usually rarely tell people to ignore advice but this is the worst I have seen in awhile.
Serious FPGA and logic development is 95% simulation. It is the only way to provide coverage over all of your test cases. Any organization who hires for serious logic development with never hire you if you don't simulate. It honestly makes you look like the bench warmer on the JV team.
Anyone who doesn't simulate either:
a.) Produces useless shit
b.) Doesn't do anything complicated.
Anything that takes a long to simulate means it takes *much longer* to synthesize. The load and go method who take so long to debug and test as synthesis cycles drive the process. When a complex piece of logic takes 2 hours to synthesize, not using the simulation tools is really dumb.
Logic analyzer tools like chipscope pro are useful as well but come *after* simulation. Even then, with a complicated design (i.e. Synthesis Times on the order of hours) debugging can be slow.
Relying on VHDL strong typing to save you is a bad idea.
I have only had 1 case in 18 years where something that something that passed all post P&R simulations that had any issues with the real world implementation. Even in that case the problem had nothing to do with the simulation not being accurate.
Simulations save an enormous amount time in the lifecycle of a project. Verilog/SystemVerilog have extremely powerful constructs for running just about anything through your logic and getting close to 100% test coverage without a human having to look at waveforms.
That all being said, if your end goal is to make led blinkers for hobby projects then you can get away with the load and go method.