Oscillator frequency vs resolution

[741]

I came across this when using a PIC16F1825 PWM. I doubled the system clock, obtaining the expected doubled max PWM frequency. Max frequency (at a fixed clock) needs the period counter PRx set to 1. I was disappointed to realise the next frequency step down (of course...) halves the frequency, back to the same frequency I had at the slower system clock speed. However, the higher the clock frequency, the better the resolution, so I gained finer intermediate steps (except at the very top end).

The higher the PRx (count of clock cycles in one PWM wave), the better the resolution. Resolution is strongly dependent upon PRx. For instance at maximum frequency (only 1 clock cycle in 1 PWM period), an increase in period of just 1 clock cycle is a 100% change in pwm period (2:1 ratio). The period doubles and the frequency halves. However, when the period is defined by 100 clock cycles, a change in period of 1 clock cycle is only a 1% change in period.

I think this has a parallel in an analog oscillator. If period is RC and C is fixed, then when R is very small, a small % change in R makes a large % change in frequency 1/(R1.C) vs 1/(R2.C).

So generally, it looks like higher frequency eventually forces lower resolution for analog or digital oscillators. Also generally, it's simply an example of the fact that a small change can be a big proportionate change.

[David Hess]

DDS (direct digital synthesis) can be used to increase frequency resolution without increasing clock speed.

[MasterT]

ST Microelectronics has HRTIM in stm32g4 product line, 5-bits delay line is increasing effective clock by factor 32. Though, 170 MHz x 32 = 5440 MHz ( 5.4 GHz !) for PWM & Input Capture.

[741]

Re DDS: Can you outline in simple terms how the resolution stays constant as f rises?

[gf]

Re DDS: Can you outline in simple terms how the resolution stays constant as f rises?

See for instance here https://www.analog.com/media/en/training-seminars/tutorials/MT-085.pdf
(Google will find various other tutorials, too)

There is of course still an upper limit for the frequency of the generated signals - see section ALIASING IN DDS SYSTEMS in the referenced document.

EDIT:

Unlinke PWM, DDS requires a DAC to produce the analog output (not just a single bit).

A single-bit-output alternative to PWM would be a delta-sigma modulator, see https://en.wikipedia.org/wiki/Delta-sigma_modulation (that's how a class D audio amplifier usually work). Besides the precision of the calculation, there is basically no limit for the frequency resolution. The actual practical limitation is rather dithering noise, i.e. the desired SNR eventually determines the required oversampling ratio (and thus the maximum signal frequency for a given clock rate).

Btw, what is actually the maximum signal frequency you want to generate, and the clock frequency? And did you already think about the amount of residual noise you are willing to accept in the generated signal (this applies to PWM too, of course)?

[gf]

A single-bit-output alternative to PWM would be a delta-sigma modulator, see https://en.wikipedia.org/wiki/Delta-sigma_modulation

In fact one had still a DDS under the hood, but replacing the DAC with a delta-sigma modulator which acts as a 1-bit DAC.

A hybrid were possible too, enhancing the 5-bit DAC of the PIC with delta-sigma modulation to a higher bit-depth.

[741]

Thanks (I infer it's not easy to explain  )

Without (yet!) having waded through the tutorial, my instinct is that actually, the max resolution is determined by the reference oscillator (and that in turn limits max frequency).

If so:
You cannot go beyond some max frequency (unless you raise the reference oscillator).
Maybe the reference oscillator actually defines resolution?

[gf]

You can increase the frequency resolution of a DDS arbitrarily by increasing the # of bits of the phase accumulator.

A higher frequency resolution does not imply a higher maximum frequency. Since the analog signal needs to be reconstructed from digital samples, the sampling theorem applies, limiting the maximum frequency. Furthermore an analog reconstruction filter after the DAC is only realizable with a limited roll-off (thus limiting the maximum frequency even further).

A higher frequency resolution also does not imply lower SNR or lower jitter or higher accuracy. E.g: If the clock drifts by 1ppm, then the generated frequency will drift 1ppm as well. If the DAC resolution is only 8 bits, then the SNR still can't be better than ~45...50dB. etc. Don't mix-up precision/resolution with accuracy! Resolution only tells at what step size you can adjust the freqency.

[PCB.Wiz]

I came across this when using a PIC16F1825 PWM. I doubled the system clock, obtaining the expected doubled max PWM frequency. Max frequency (at a fixed clock) needs the period counter PRx set to 1. I was disappointed to realise the next frequency step down (of course...) halves the frequency, back to the same frequency I had at the slower system clock speed. However, the higher the clock frequency, the better the resolution, so I gained finer intermediate steps (except at the very top end).

The question is not well worded, but for PWM systems, the ultimate granularity for 8b MCUs is usually the PWM Clock.
There are higher end chips than PIC16F1825, that use delay lines as well as counters, and those can get PWM step sizes in the sub-ns levels.

Some 8b MCUs use a PLL on the PWM, so they can offer 64MHz or 128MHz or 144MHz PWM clocks, and usually lower CPU clocks.

DDS designs output an average frequency, usually a sine wave. So they are not used for PWM.
The edge granularity on DDS is the adder rate, so that's much slower than SysCLK on 8b MCUs (more like 1/8th~1/20th), but that can average over many periods to give an accurate average frequency. 
Dedicated DDS HW runs the adder at the clock rate, and the more you pay, the better the specs

[NorthGuy]

If you measure PWM resolution in units of time, then it doesn't depend on the frequency. Say, your PIC16's resolution is the command clock period divided by 4 - roughly 30 ns. If there's no limitations, the maximum PWM frequency would be 2/t where t is the resolution - which would be produced if you toggle the pin as fast as you can giving you 50% duty cycle. Would be 16 MHz in your case, but PIC16 cannot do this - 8 MHz is the best.

Newer dsPIC33 have 250 ps PWM resolution - 1000 times better than PIC16.

[gf]

If you measure PWM resolution in units of time, then it doesn't depend on the frequency. Say, your PIC16's resolution is the command clock period divided by 4 - roughly 30 ns.

If for instance 4096 analog levels were required (corresponding to a 12 bit DAC), then 30ns lead to a PWM frequency of ~8kHz. So the maximum frequency of the signal which can be carried by the PWM is 4kHz then (in practice lower since the reconstruction filter has a limited roll-off). Renouncing analog levels  increases the PWM frequency, but at the cost of higher quantization noise. There is no free lunch...

[NorthGuy]

If you measure PWM resolution in units of time, then it doesn't depend on the frequency. Say, your PIC16's resolution is the command clock period divided by 4 - roughly 30 ns.

If for instance 4096 analog levels were required (corresponding to a 12 bit DAC), then 30ns lead to a PWM frequency of ~8kHz. So the maximum frequency of the signal which can be carried by the PWM is 4kHz then ...

12-bit resolution with 32 MHz switching will produce 8 kHz frequency. 16-bit resoulution will produce 500 Hz frequency. 8-bit resolution will produce 500 kHz frequency. And so on ...

All this enchilada can be characterized by a single number - time resolution of the switching - 30 ns.

[741]

The edge granularity on DDS is the adder rate

Suppose I wanted a 0.01Hz to 1MHz oscillator (not pwm), frequency resolution 1% worst case (0.0001Hz).

So I can set 0.01Hz, 0.02Hz....99999.99Hz, 1000000.00Hz

What adder rate is required?

[PCB.Wiz]

The edge granularity on DDS is the adder rate

Suppose I wanted a 0.01Hz to 1MHz oscillator (not pwm), frequency resolution 1% worst case (0.0001Hz).

So I can set 0.01Hz, 0.02Hz....99999.99Hz, 1000000.00Hz

What adder rate is required?

You need to choose also how many steps you need per 1MHz cycle.
Let's choose some common numbers, like 25MHz adder rate and 32b adder.

 fa=25M*(round(2^32*(1M/25M)))/2^32 = 1000000.0009313
and the next step from there is
 fb=25M*(1+round(2^32*(1M/25M)))/2^32  = 1000000.00675208866596221923828

 fa-fb = -0.005820
Which is in the same ballpark as your 10mHz step size, just a bit smaller.  A 50MHz adder is  11.16mHz step size on 32b adder word.

That leads to
 fADD = 42.94967296MHz

 fb=fADD*(1+round(2^32*(1M/fADD)))/2^32 = 999999.99
 fa=fADD*(round(2^32*(1M/fADD)))/2^32 = 1000000
 fa-fb = 0.01, or your 10mHz step.

[741]

Thanks for the worked example . Can I reduce the 32 bit adder size and what effect would that have? Assume it does not matter wheher the ouput is sine or square etc

[PCB.Wiz]

Thanks for the worked example . Can I reduce the 32 bit adder size and what effect would that have? Assume it does not matter wheher the ouput is sine or square etc

Sure, just change the '32' in the equations above to any number you like, and you can see the new step size, given an adder MHz.
Note that DDS systems give precise average frequencies, but the sampling jitter is still set by the adder MHz.
If you want a 'better' square wave, you get less jitter if you first generate a sine, pass via a good low pass filter, to remove the steps,  and then slice that. 

[gf]

Thanks for the worked example . Can I reduce the 32 bit adder size and what effect would that have? Assume it does not matter wheher the ouput is sine or square etc

The sampling theorem tells you that you need a sampling rate of > 2MHz for a max. signal frequency of 1 MHz. So for 10mHz resolution the theoretical maximum you could reduce were 4 bits (from 32 to 28), by reducing the clock frequency (sampling rate) by a factor of 2⁴ from 42.94967296 to 2.6844 MHz (which is still > 2 MHz then). This would require an analog low-pass reconstruction filter with a very steep cut-off, though, which is difficult to realize. Saving just 4 bits is IMO not worth the complications. For practical reasons I'd rather stay with a 32 bit accumulator, and a clock of at least 10 MHz (i.e. significantly larger than the largest signal frequency), allowing a simpler reconstruction filter.

Although DDS can basically generate arbitrary periodic waveforms, generating a square wave results in significant jitter in the amount of 1/f_clock for frequencies which are not an integral fraction of the half clock frequency. The DAC is de facto degraded to a 1-bit DAC in this case, since it is only fed with two different values, one for "high" and one for "low". If a low-jitter square wave output from a DDS is desired, then I'd rather tend to generate a sine wave in the first place, and apply a zero-crossing comparator after the reconstruction filter. Depends of course on the amount of jitter you can tolerate, and the ratio between max. signal frequency and clock frequency. If your clock has say 40 MHz and you can tolerate 25ns jitter, then directly generating a square wave via DDS is well possible. You do not even need a DAC then, but only a single-bit output, and you can even renounce a reconstruction filter.