Can I see the source code of your sync generator....
module vga_control( CLK, //CLK input
ENABLE, //enable module
RESET, //resets device
VGA_CLK, //pixel clock for vga
VGA_X, //x position of vga
VGA_Y, //y position of vga
VGA_HS, //horizontal sync
VGA_VS, //vertical sync
VGA_VISIBLE, //are we in visible region
VGA_RED, //4 bit red colour
VGA_BLUE, //4 bit blue colour
VGA_GREEN); //4 bit green colour
input wire CLK, ENABLE, RESET;
wire VGA_HS, VGA_VS, VGA_VISIBLE;
output wire VGA_CLK, VGA_HS, VGA_VS, VGA_VISIBLE;
output reg [11:0] VGA_X, VGA_Y;
output wire [3:0] VGA_RED, VGA_BLUE, VGA_GREEN;
//HP1662AS PARAMETERS (17.36MHz clock)
parameter H_TOTAL = 695;
parameter H_SYNC_PULSE = 56;
parameter H_VISIBLE = 500;
parameter H_FRONT_PORCH = 18;
parameter H_BACK_PORCH = 121;
parameter V_TOTAL = 417;
parameter V_VISIBLE = 378;
parameter V_SYNC_PULSE = 3;
parameter V_FRONT_PORCH = 11;
parameter V_BACK_PORCH = 25;
//Line doubled (34.720MHz clock)
/*parameter H_TOTAL = 695;
parameter H_SYNC_PULSE = 56;
parameter H_VISIBLE = 500;
parameter H_FRONT_PORCH = 18;
parameter H_BACK_PORCH = 121;
parameter V_TOTAL = 834;
parameter V_VISIBLE = 756;
parameter V_SYNC_PULSE = 6;
parameter V_FRONT_PORCH = 22;
parameter V_BACK_PORCH = 50;*/
//generate clock (change clock for different display modes)
wire PLL_LOCKED;
//generate vga clock
clk_wiz_17360 vga_clk( .clk_out1(VGA_CLK),
.reset(RESET),
.locked(PLL_LOCKED),
.clk_in1(CLK));
//set VGA_VISIBLE high when we are in the visible portion of the image
assign VGA_VISIBLE = (VGA_X >= H_SYNC_PULSE + H_BACK_PORCH) && (VGA_X < H_VISIBLE + H_BACK_PORCH + H_SYNC_PULSE) && (VGA_Y >= V_SYNC_PULSE + V_BACK_PORCH) && (VGA_Y < V_VISIBLE + V_SYNC_PULSE + V_BACK_PORCH);
assign VGA_HS = ~(VGA_X < H_SYNC_PULSE);
assign VGA_VS = ~(VGA_Y < V_SYNC_PULSE);
assign VGA_RED = (VGA_VISIBLE ? 15 : 0); //red whenever we are in visible region
assign VGA_GREEN = ((VGA_VISIBLE && ((VGA_X == H_SYNC_PULSE + H_BACK_PORCH) || (VGA_X == H_VISIBLE + H_BACK_PORCH + H_SYNC_PULSE - 1))) ? 15 : 0); //green/red vertical edges
assign VGA_BLUE = ((VGA_VISIBLE && ((VGA_Y == V_SYNC_PULSE + V_BACK_PORCH) || (VGA_Y == V_VISIBLE + V_SYNC_PULSE + V_BACK_PORCH - 1))) ? 15 : 0); //blue/red horizontal edges
//at every clock edge
always @(posedge VGA_CLK)
begin
//if enabled
if(ENABLE) begin
//increment VGA_X and VGA_Y
if(VGA_X < H_TOTAL - 1) begin
VGA_X <= VGA_X + 1;
end else begin
VGA_X = 0;
if(VGA_Y < V_TOTAL - 1) begin
VGA_Y <= VGA_Y + 1;
end else begin
VGA_Y <= 0;
end
end
end
if(RESET) begin
VGA_Y <= 0;
VGA_X <= 0;
end
end
endmodule
Not bad, simple and compact. If you would take my recommendation, I would recommend these alterations, which may help alleviate you horizontal/vertical picture alignment bug. (maybe, the problem may be elsewhere which we can discover with another test...)
1. Make vga_visible (for H&V) = (VGA_X < H_VISIBLE) && (VGA_Y < V_VISIBLE)
Ahhhhh, now your outputs VGA_X and VGA_Y are your actual output visible X&Y coordinates. Now, for the X, you can use these to feed the address of your dual-port line buffer memory on the output side.
2. Make VGA_HS = (VGA_X >= H_VISIBLE + H_FRONT_PORCH ) && (VGA_X =< H_VISIBLE + H_FRONT_PORCH + H_SYNC_PULSE) ;
3. Do the same for VGA_VS.
******** You should only bother going further below this point if you want a real-time software controllable video output generator.
Though, thanks to compiler optimizations, and you are using fixed parameters, your current code works out simple and compact, but, if you want to adjust in real time the video positioning, in one of my old codes, I basically had in the counting loops this:
4 additional latched input regs, HS_start, HS_stop, VS_start, VS_stop, VGA_HS&VS are now output regs instead of wires...(Actually, I personally prefer everything coming out of my modules to be regs so that feeding IOs directly make extra clean clear cut clock timing):
Inside the @posedge clk/if(VGA_X < H_TOTAL - 1) begin
if (VGA_X = HS_start) begin
VGA_HS <= 1;
end else if (VGA_X = HS_stop) begin
VGA_HS <= 0;
end
The reason for not placing all the adds and sums inside the '(VGA_X = HS_start)' is since these are no longer constants for the compiler to figure out before wiring logic, any math performed gets converted into gates, versus a simple equality comparator. Same goes for the adding a latched reg input for H_TOTAL and H_VISIBLE and of course all the Vertical factors. Having input latched regs gives you that 1 input 14 bit data buss with 3 bit address & WE making 8 internal regs to be latched to create any video format you like.
I know there seems to be only 8 variables of consequence H_total, H_active, HS_start, HS_stop, + VS versions, but you might add 2 more later-on, something like H_genlock & V_genlock which will allow you to set an adjustable offset between the source video frame and the output video frame. These could be tied into the counters + 1 & an external additional HS&VS input into this module.