If it is useful, here is a dump of all the registers o the TVP, starting from address 0x00.
02 69 80 A0 00 06 10 20 00 00 00 80 83 80 52 2E
5D 20 01 00 B5 04 11 02 00 00 C2 77 07 00 10 10
10 0D 08 12 6B 10 80 0C 53 08 07 00 50 00 80 8C
04 5A 18 60 03 10 00 00 20 69 00 07 00 03 04 00
2C 01 2C 06 05 05 1E 1E 00 00 E3 16 4F 02 CE 06
AB F3 00 10 55 FC 78 F1 88 FE 00 10.
Can you break this down into control names starting on page 26 of TI's datasheet?
Example:
02 = Chip revision.
69 8 = pll-divider = 1688 (This means you set the chip to sample 1688 pixels from H-sync to H-Sync)
1688 * 25Khz = 42200Khz, or, 42.2MHz. You said 108MHz, this isn't right.
ADR $03 = A0 = Oscillator = 10 = 70-135MHz, and, 100 = charge pump current just below default.
Change this from $A0 to $60 if you are indeed running at 42.2MHz.
00 = Sampler phase
06 = Clamp start - The point in the picture to DC clamp the input capacitor to black level reference. Make sure external clamp is disabled otherwise the video may clip to all 100% white or all 100% black.
10 = 16 = clamp width - The duration of this clamp.
20 = Hsync output width of 32 pixels.
Adr...0E = 52 = #01010010
HSPO: HSYNC polarity override 0 = Polarity determined by chip (default)
HSIP: HSYNC input polarity 1 = Indicates input HSYNC polarity active high (default)
HSOP: HSYNC output polarity 0 = Active low HSYNC output (default)
AHSO: Active HSYNC override 1 = Active HSYNC is manually selected via the AHSS control bit (bit 3 of register 0Eh). (default)
AHSS: Active HSYNC select. 0 = Active HSYNC is derived from the selected HSYNC input
VSOP: VSYNC output polarity 0 = Active low VSYNC output (default)
AVSO: Active VSYNC override 1 = Active VSYNC is manually selected via the AVSS control bit (bit 0 of register 0Eh). (default)
AVSS: Active VSYNC select. 0 = Active VSYNC is derived from the selected VSYNC input
Are the read-back of HS polarity and VS polarity true? Bit 6 for HS and Bit
--------------------------------
Change ADR $10 from $5D to $58. No big difference here since you are not using Red and Blue.
Readback adr $14 seems OK.
Try switching:
ADR $22 to = 02.
ADR $26 to = 0. (Must be disabled for your scopes weird non-standard video format.)
ADR $2F should be 0C. Your read 8C may just be the undefined reserve bits.
Readback address $38 = 20, this is a semi-good sign, ADR$37 = 00 is a bad sign. The IC isn't counting the number of lines in a frame... If the IC working on the video V-sync and H-Sync, unless I misunderstood these 2 read only registers.
Readback address $39 and $40, = $069 = 105 = 27mhz / 105 = 257142.8571 hz, or, 257 Khz??? Is this correct, isn't your video around 25.7Khz? Or, if you are using the IC internal 6.3 MHz clock reference, we get 60KHz?
These 2 read-backs say something may be wrong with the ICs 27MHz reference system clock or the syncs coming in aren't being read properly, or the IC's internal 6.3MHz clock
Readback ADR $3B is 7 - H-sync size.
Readback ADR $3D = 0 - This is telling us your V-Sync is 0 lines long. This is obviously wrong. Again, it is a sign that the IC doesn't see the VS or HS properly....
Also, make sure that reset pin is held low during power-up for a bit of time before making it high.
What are you reading on the green data port, all high, or all low. If you are getting all high, then the ADC may be working fine and all we need to do is debug the clamp position setting after you look at my above changes.
Probe pins 81 and 78 directly, see if your syncs are getting there.
Also, scope the video going into the TVP IC, tell me what the voltage offset is.