FGPA cost / market

[Stonent]

I was looking at FPGAs on Mouser and notice that some cost in the thousands of dollars (I'm assuming each). Is that truly the cost for a high end device?

What's the intended market for devices of that level of complexity? Just big time number crunching?

[Fsck]

as well as asic simulators.

[marshallh]

A $40k fpga is much cheaper and doesn't take months like an asic one-off

[Stonent]

A $40k fpga is much cheaper and doesn't take months like an asic one-off

I guess that's what the market will bear for a special device.

It would seem the FPGAs themselves are not that complex from a design standpoint once you have a cell built. Just keep repeating it over and over again and grow the FPGA bigger and bigger until it reaches a size that is no longer feasible for the customer to implement.

[Fsck]

also any high bandwidth applications like 100G/400G networking for their high throughput transceivers (the high end models)

[amyk]

It would seem the FPGAs themselves are not that complex from a design standpoint once you have a cell built. Just keep repeating it over and over again and grow the FPGA bigger and bigger until it reaches a size that is no longer feasible for the customer to implement.

The reason for the huge costs is yield - these monster FPGAs have huge die, and since the probability of defects is proportional to the area, it becomes much harder to make a single perfect die as it becomes bigger.

A $40k fpga is much cheaper and doesn't take months like an asic one-off

It's also reusable.

[mikeselectricstuff]

It would seem the FPGAs themselves are not that complex from a design standpoint once you have a cell built. Just keep repeating it over and over again and grow the FPGA bigger and bigger until it reaches a size that is no longer feasible for the customer to implement.

The reason for the huge costs is yield - these monster FPGAs have huge die, and since the probability of defects is proportional to the area, it becomes much harder to make a single perfect die as it becomes bigger.

A $40k fpga is much cheaper and doesn't take months like an asic one-off

It's also reusable.

Even with  a good yield, it's a big die and you don't get so many on the wafer. Test times on large chips also become a significant cost.

[Kohanbash]

There are also specialty FPGA's that have a large price tag. For example the space rated ones (ie rad hard).

[slateraptor]

I know I student that used an FPGA in the price range of 2k$ and I almost couldn't believe it. Just after checking Farnell I did. He used graphical language to program it, compile source for teleoperation "haptic feedback".

Anybody used something like this?

Used an older (now obsolete) $10k-ish PCI-X card from Nallatech for a graduate-level course in reconfigurable computing a few years ago back in uni. Board was physically installed in a server which was part of a HPC cluster. VHDL synthesis/place+route in Xilinx ISE (an intentionally older version due to license restrictions in latest release at the time), ModelSim for simulation testbenching, card top-level block interconnect using Nallatech proprietary software (the GUI part), raws uploaded to server and C++ written for I/O testing of whatever concept was the focus that week. Several 1- to 4-week-long "labs" that semester (wasn't actually a lab course, but nobody gave a flying fuck either way), with each goal increasing in complexity; for last "lab", typical synthesis/place+route times were a painful 2 hrs+ and clocks were all over the place by requirement, with a few at 200MHz. Topics were a solid mix of both theoretical (like 1D/2D pipeline architectures and optimization heuristics) and practical (like cross clock domain mitigation techniques and DDR memory interfacing). Ironically, quite a bit of cheating amongst (overwhelmingly not US) grads (was one in a handful of undergrads). 2nd best professor I had, best course ever. *insert nostalgia here*

IDK WTF I'm wasting my time in current ball-and-chain-industry and not chasing FPGAs like a band of topless sorority girls.

[marshallh]

IDK WTF I'm wasting my time in current ball-and-chain-industry and not chasing FPGAs like a band of topless sorority girls.

I do that and somehow made it so I can fund my escapades with more fpga work
It ain't all pretty though.. Grass is greener and all that. Beats SW by a long shot, imo

[EEVblog]

I was looking at FPGAs on Mouser and notice that some cost in the thousands of dollars (I'm assuming each). Is that truly the cost for a high end device?

Yep, some go into the 5 figure range per chip.
They use high end process technology and the dies are some of the biggest in the business, not to mention testing the beasts. That adds up to big $$$$ per chip, even without factoring in NRE.

[marshallh]

Here is a low end Stratix III (I think this one is on digikey for ~4k)
Pardon the poor lighting, I tried to get a shot of the die under the heatspreader. It is close to a square inch in area.
The dies are binned into usually 3 or 4 speed grades. The faster grades cost a good deal more than the slowest one.

[Alex]

I remember hearing/reading of Intel using exotic FPGAs to test out designs.

Don't quote me on this but certainly a pointer for further research.

[marshallh]

This is what Intel/AMD and some others use for testing out asic designs. IIRC they are full of racks upon racks of FPGAs.
They run software that partitions the netlist into physical blocks and interconnects them. Of course this will run an order of magnitude slower than the final thing but it's sufficient.



Smaller designs may be partitioned across a single protoboard with 4-16 high end Stratix/Virtex fpgas.

http://www.cadence.com/Community/blogs/ii/archive/2011/06/01/q-amp-a-a-closer-look-at-the-rapid-prototyping-platform.aspx

[EEVblog]

I remember hearing/reading of Intel using exotic FPGAs to test out designs.
Don't quote me on this but certainly a pointer for further research.

Start here and work your way up:
http://www.dinigroup.com/new/products.php

[mike_la_jolla]

I remember hearing/reading of Intel using exotic FPGAs to test out designs.
Don't quote me on this but certainly a pointer for further research.

Start here and work your way up:
http://www.dinigroup.com/new/products.php

-- The BIG FPGAs are thousands of dollars and some can get to $10k/each.  Products based on these expensive devices are used to prototype ASICs.  They are too expensive to deploy in 'products'.  A common application, for example, is to use an FPGA Prototype to test head-end cell phone algorithms with real data (CMDA, GSM).  The Cadence Palladium pictured above is 10x-100x too slow to do this.  Prototyping graphics is very common also.

-- Intel, Qualcomm et al use these big FPGAs.  They are a huge customers of Xilinx and Altera.

-- Here is the biggest commercial FPGA card ever built:  http://www.dinigroup.com/new/DN7020k10.php.    This card is now obsolete.  List price with 20 4SE820 FPGAs was ~$200k.  Larger cards have been build by internal teams at several companies.  This is hard, very specialized stuff.

-- Algorithmic acceleration using FPGAs, talked about above using Nallatech boards is a 'solution looking for a market'.  It turns out that there aren't that many applications that can compete against a grid of GPUs and 4 lines of CUDA.  'C' to FPGA methodologies are a bit silly.

I'd be happy to answer any other questions on FPGAs.  The information posted here is refreshingly correct.  You'd never believe the conversations I've had with those fools trying to do Bitcoin mining ...

[tszaboo]

As I've already said, digikey pricing has nothing to do with real price, when it comes to FPGA-s. Just look at the recent Nvidia G-sync.
http://www.anandtech.com/show/7582/nvidia-gsync-review/3
That ARRIA V GX is priced at least 530 dollars at digikey, while the whole board is only 120 dollars. I'm almost sure ASUS or Nvidia does not sell this with loss.

[flynnjs]

> It turns out that there aren't that many applications that
> can compete against a grid of GPUs and 4 lines of CUDA.

Don't really agree there. There's a whole heap of stuff that
can benefit from riduculously long pipelines which you can't
achieve on CPU or GPU.

[mike_la_jolla]

> It turns out that there aren't that many applications that
> can compete against a grid of GPUs and 4 lines of CUDA.

Don't really agree there. There's a whole heap of stuff that
can benefit from riduculously long pipelines which you can't
achieve on CPU or GPU.

I specialize in this area and can't name 5 reasonable applications.  That is less than a 'whole heap of stuff'.   Maybe I'm missing something.   Could you elaborate?

[alex.forencich]

> It turns out that there aren't that many applications that
> can compete against a grid of GPUs and 4 lines of CUDA.

Don't really agree there. There's a whole heap of stuff that
can benefit from riduculously long pipelines which you can't
achieve on CPU or GPU.

I specialize in this area and can't name 5 reasonable applications.  That is less than a 'whole heap of stuff'.   Maybe I'm missing something.   Could you elaborate?

How about real time digital beamforming for a phased array radar?  Although that doesn't have too many applications outside of defense, I suppose.  Any super heavyweight realtime DSP type stuff is far better suited to FPGAs than to GPUs.  GPUs can crunch numbers well, but they are horrible for high speed I/O.  Also, reconfigurable line rate packet processing at 10 Gbps or faster is a very good application for FPGAs. 

[krenzo]

To name a few more: checksumming and encryption/decryption of large files (depending on the algorithm)

[mike_la_jolla]

To name a few more: checksumming and encryption/decryption of large files (depending on the algorithm)

Nope.  The overhead of moving data to the accelerating engine in the FPGA doesn't justify the gain in speed.

[lorth]

  You'd never believe the conversations I've had the those fools trying to do Bitcoin mining ...

Can you elaborate on this? I'm curious....

[mike_la_jolla]

  You'd never believe the conversations I've had the those fools trying to do Bitcoin mining ...

Can you elaborate on this? I'm curious....

Go here to start.  I'd be happy to elaborate if you'd like:  http://www.dinigroup.com/diniblog/?p=120

[NiHaoMike]

How about real time digital beamforming for a phased array radar?  Although that doesn't have too many applications outside of defense, I suppose.

Automotive radar (self driving cars and crash avoidance) would be one consumer level use of such technology, though they'll almost certainly use ASICs once such technology gets to mass production.