A55 interrupt latency

[glenenglish]

Anyone got any data on Cortex A55 minimum interrupt latency ? Cant find anyting in the ARM tech manual.
In non virtualized mode. Private moderate sized core speed L2 would enable  the critical IRQ service  code  to be locked there.... leaving only the bus and GIC latency ? I dont know a whole lot about the GIC inner workings.

Altera are making a strong pitch to me with their new Agilex 5, has A76/A55. I'd be converting from my A53/R5 cores on the MPSoC.
On MPSoC, the R5 cores with their private TCM and own AXI in the LPD have low latency. Of course you are at the overall bus mercy, depending on where the fabric produced data (the irq source etc)  is dumping the data into.....and still doesnt compare to the latency
 performance of a softcore in fabric with BRAM memory with overall irq latency of a few cycles.

My (arse) guess is that Altera are expecting you to drop a NIOS soft core if you need low latency .
-glen