Already hinted in 2021 when some advanced info "leaked" in MPLABX IPE, but now it's official.
XC-DSC v3.10 added a lot of information in the compiler manual about dsPIC33A, including
- 32bit architecture, as the size of register becomes 32bit
- FPU (mentioning of F0-F31 registers in context swap)
- Unified Memory space (32bit address space, meaning no more PSV and EDS)
- While still remaining a DSP with a rich set of addressing mode
- First 64k are near data space, meaning that many instructions can operate directly on memory instead of doing Load/Store
And while skimming the US MASTERS program.. wow
This class introduces the features and architecture of the dsPIC33A family of devices. Content includes core features and use of select peripherals including 40 MPSP ADC, floating point unit, and high resolution PWM. Differences and advantages from earlier dsPIC33 devices are presented along with application examples. Attendees will gain understanding of the dsPIC33A family of devices and their capabilities.
In this class you will see and experience the latest innovations in a new 200 MHz Digital Signal Controller including double precision floating point unit, 32-bit instruction and data paths with dual 72-bit accumulators together with a suite of fast peripherals designed to accelerate your real-time applications. This class will explore fast signal acquisition and related signal processing in a new and robust manner with Microchip's latest dsPIC family of devices. Material included will utilize this device for a rudimentary digital storage oscilloscope and then process these input into the frequency domain using FFTs using this processor core.
so 40MSPS ADC (and the ADC in the dsPIC series is
good)
and 72bit DSP
(and MPLABX migrating to VS Code / Eclipse. Godspeed Netbeans, hope this won't be a worse disaster)
https://techtrain.microchip.com/usmasters/classes.aspxAh, i wish they will do EU Masters..