dsPIC33A: new 32bit DSP!

[NorthGuy]

Well it arrived today... just don't make the same mistake I did: order one of the MCU DIM modules EV18H47A and/or EV02G02A too, otherwise you have a paperweight, and not a very heavy one either.

I ordered a couple of  EV68M17A. Looks like they have programming/debugging connectors. Should be enough to figure out how it all works.

[Howardlong]

Well it arrived today... just don't make the same mistake I did: order one of the MCU DIM modules EV18H47A and/or EV02G02A too, otherwise you have a paperweight, and not a very heavy one either.

I ordered a couple of  EV68M17A. Looks like they have programming/debugging connectors. Should be enough to figure out how it all works.

Turns out I got the DIM part number dramatically wrong somehow.I ordered EV68M17A and EV67K87A.

[JPortici]

New document has appeared - a migration guide. It explains few things. Instruction times are definitely subject to instruction bus wait and SFR wait. SFRs have various access time and may run 1:1, 1:2, 1:4 to system clock. The instruction clock is the same as the oscillator (was 2:1). Does it mean that simultaneous read/write in the same instruction will require 2 cycles? 2kb (512 instructions) cache for instruction flash fetches. How fast is it without cache? Can cache be controlled? Can execute from RAM for faster execution. But is it subject to bus contention with data fetches? Overall it looks like predictability was sacrificed for faster CPU clock.

Other than that lots of improvements, practically everywhere.

I've read that!
hm... would be interesting to compare against M4F (and maybe M7? though they come with such high clock frequency it's probably pointless...)
Why did they say dsPIC33C is 1 step pipeline? Isn't it 2 step pipeline (Fecth/Execute)?

> Execute from RAM
yes!!!

Tomorrow i'll try to see if FAE are still a thing here in italy, i'd like to see a datasheet and prices because there could be many new features i'd want to have in a new series of products, mainly security, and i don't really want to wait to mid september for masters... only to find out i can't use them (that document mentions no SCCP for the first series of devices, i need many independent channels, and i'm not sure i can coerce the PWM module into that... they surely can't do input capture)

[Howardlong]

New document has appeared - a migration guide.

I've read that!

My Google foo clearly isn't up to it, do you have a reference please?

[NorthGuy]

My Google foo clearly isn't up to it, do you have a reference please?

I searched for dsPIC33A on Microchip Website (this method was suggested by one of the early posters here). Here's the direct link:

https://ww1.microchip.com/downloads/aemDocuments/documents/MCU16/ProductDocuments/SupportingCollateral/dsPIC33CK-to-dsPIC33AK-Migration-and-Performance-Enhancement-Guide-DS70005574.pdf

[uer166]

Looks like upper end devices have up to to 5 ADC cores at 40MSPS. That is quite useful! (Even though CPU can't process all at 40MSPS obviously)

[marcov]

In case you haven't seen, some more datasheets on the microchip site

https://www.microchip.com/en-us/search?searchQuery=dspic33a&category=ALL&fq=start%3D0%26rows%3D19

The one from the curiosity board seems to have 16kb ram

[JPortici]

In case you haven't seen, some more datasheets on the microchip site

And Erratas... None is a dealbreaker to me, phew

[Howardlong]

A short vid has just appeared, that, like many Microchip videos, are too short to offer anything more than the most minimal amount of information.

https://youtu.be/AOySt6iHVw8?si=KtqgQqtwhDfgADhN

[iMo]

There are 800-1500 pages long datasheets to download, afaik..

PS: hopefully at least 3-4 ADCs are simultaneously sampling..

[Howardlong]

There are 800-1500 pages long datasheets to download, afaik..

PS: hopefully at least 3-4 ADCs are simultaneously sampling..

They seem to have dropped the datasheet + FRM method, where you often end up referring to multiple documents, and have to figure out anything different between datasheet and FRM.

The current chips have two ADCs for simultaneous sampling.

Fastest Tad is 12.5ns (80MHz derived from a 320MHz clock, using the ADC's fixed divide-by-4), parameter AD50 on Table 37-40 p1484, document DS70005539B.

Sampling time Tsamp for 12 bits must be 9ns minimum (assuming typical internal Ric = 1k ohm and Chold = 1pF, and negligible source impedance, AD60 & AD62 on Table 37-40 p1484). The next available sample time is 31.25ns, from Section 15.3.6 p851.

Conversion time Tconv is 1.5 Tad, or 18.75ns irrespective of the number of conversion bits you need, it always converts 12 bits. Section 15.4.3 p865.

Tconv + Tsamp = 50ns, so 20MHz sample rate is maximum rate for 12 bits (also applies if you're only interested in 9, 10 and 11 bits).

If you want to do an in-spec conversion at minimum Tsamp (6.25ns) and Tconv (1.5 Tad or 18.75ns), 8 bits is the maximum effective resolution (it still converts 12 bits, but only up to 8 bits are reliable).

[JPortici]

They seem to have dropped the datasheet + FRM method, where you often end up referring to multiple documents, and have to figure out anything different between datasheet and FRM.

Hope not, i'd like to have an in depth description of the security module with examples (hopefully some application notes will come..) as it was the custom with the FRM chapters

[Howardlong]

It's here!

Did a blinky, got it running at 200MHz, although the fastest I've been able to toggle a pin is about 33MHz. I'd have expected to toggle at 50MHz as the standard peripheral bus is Fcy/2.

I've already encountered a handful of errors in the datasheet so far, in particular regarding the PLL example code.

I'll put more info up on Microchip dsPIC33 forum.

[coppice]

I've already encountered a handful of errors in the datasheet so far, in particular regarding the PLL example code.

MCU example code that doesn't work? I'm shocked.

[glenenglish]

Tconv + Tsamp = 50ns, so 20MHz sample rate is maximum rate for 12 bits (also applies if you're only interested in 9, 10 and 11 bits).
If you want to do an in-spec conversion at minimum Tsamp (6.25ns) and Tconv (1.5 Tad or 18.75ns), 8 bits is the maximum effective resolution (it still converts 12 bits, but only up to 8 bits are reliable).

Any numbers of full power bandwidth and ENOB ?

[Howardlong]

Tconv + Tsamp = 50ns, so 20MHz sample rate is maximum rate for 12 bits (also applies if you're only interested in 9, 10 and 11 bits).
If you want to do an in-spec conversion at minimum Tsamp (6.25ns) and Tconv (1.5 Tad or 18.75ns), 8 bits is the maximum effective resolution (it still converts 12 bits, but only up to 8 bits are reliable).

Any numbers of full power bandwidth and ENOB ?

Not specified and 10.5 bits.

[kilohercas]

I am having difficulty understanding the discrepancy between the specifications and the promotional material. The datasheet specifies a 2.5 ns PWM resolution, whereas the promotional video claims a 78 ps resolution. However, I was unable to find any supporting data for the higher resolution PWM. The 78 ps PWM step would be very intriguing for me, especially in the context of eGaN devices.

[coppice]

I am having difficulty understanding the discrepancy between the specifications and the promotional material. The datasheet specifies a 2.5 ns PWM resolution, whereas the promotional video claims a 78 ps resolution. However, I was unable to find any supporting data for the higher resolution PWM. The 78 ps PWM step would be very intriguing for me, especially in the context of eGaN devices.

You need something like 78ps to be competitive in the control market these days. They are all doing it since the C2000 started the trend.

[Howardlong]

I am having difficulty understanding the discrepancy between the specifications and the promotional material. The datasheet specifies a 2.5 ns PWM resolution, whereas the promotional video claims a 78 ps resolution. However, I was unable to find any supporting data for the higher resolution PWM. The 78 ps PWM step would be very intriguing for me, especially in the context of eGaN devices.

You need a PWM peripheral with "Fine edge placement" in Microchip terms. The currently documented dsPIC33A devices don't have this feature. *

In their other dsPIC33's with this feature, they go down to 250ps resolution, but it dictates a specific clock frequency as it relies on a fixed multi-tapped delay line for the last 3 bits of resolution.

* Edit: For some reason I missed the "don't" out. Doh!

[JPortici]

I am having difficulty understanding the discrepancy between the specifications and the promotional material. The datasheet specifies a 2.5 ns PWM resolution, whereas the promotional video claims a 78 ps resolution. However, I was unable to find any supporting data for the higher resolution PWM. The 78 ps PWM step would be very intriguing for me, especially in the context of eGaN devices.

the currently available device does not have the high speed mode (fine edge placement) so it should be only 400MHz
I see mention of this 78ps resolution for an upcoming "second generation" device in the "dsPIC33C to dsPIC33A Migration guide"

[Howardlong]

I am having difficulty understanding the discrepancy between the specifications and the promotional material. The datasheet specifies a 2.5 ns PWM resolution, whereas the promotional video claims a 78 ps resolution. However, I was unable to find any supporting data for the higher resolution PWM. The 78 ps PWM step would be very intriguing for me, especially in the context of eGaN devices.

the currently available device does not have the high speed mode (fine edge placement) so it should be only 400MHz
I see mention of this 78ps resolution for an upcoming "second generation" device in the "dsPIC33C to dsPIC33A Migration guide"

Correct, I don't know how I missed the *don't* bit out, but you're right, that is exactly what I meant.

Regarding forthcoming devices, I expect to see ethernet as there's an RMII interface on the EV74H48A Curiosity dev board. USB 2.0 HS would be a choice of mine.

[JPortici]

I am having difficulty understanding the discrepancy between the specifications and the promotional material. The datasheet specifies a 2.5 ns PWM resolution, whereas the promotional video claims a 78 ps resolution. However, I was unable to find any supporting data for the higher resolution PWM. The 78 ps PWM step would be very intriguing for me, especially in the context of eGaN devices.

the currently available device does not have the high speed mode (fine edge placement) so it should be only 400MHz
I see mention of this 78ps resolution for an upcoming "second generation" device in the "dsPIC33C to dsPIC33A Migration guide"

Correct, I don't know how I missed the *don't* bit out, but you're right, that is exactly what I meant.

Regarding forthcoming devices, I expect to see ethernet as there's an RMII interface on the EV74H48A Curiosity dev board.

Unless it comes with an SPI controller/phy

USB 2.0 HS would a choice of mine.

Same. USB full speed for bog slow PIC24, but not anymore for dsPIC, or PIC18 for that matter. I've been asking that for years..

[PCB.Wiz]

the currently available device does not have the high speed mode (fine edge placement) so it should be only 400MHz
I see mention of this 78ps resolution for an upcoming "second generation" device in the "dsPIC33C to dsPIC33A Migration guide"

Can they capture to 400MHz/2.5ns as well, or is that 2.5ns only PWM out ?

[NorthGuy]

USB full speed for bog slow PIC24, but not anymore for dsPIC, or PIC18 for that matter. I've been asking that for years..

Yes, USB HS would be great for dsPIC33, but, they don't even use USB FS. If you compare dsPIC33A with PIC32MZ. Both running at 200 MHz. Home come PIC32MZ gets its USB HS while dsPIC33A doesn't.

[SiliconWizard]

I guess the market is just not there? It's interesting to see that USB HS is still a rarity in MCUs and usually reserved for the "performance" ones (like Cortex-M7 based) with very few exceptions, especially if you're looking for one with an integrated PHY.

That's one point which makes me like the CH32V30x.