Arm currently offers a $40k fast track license for the cortex m0 (
http://www.arm.com/products/designstart/index.php), which is quite expensive. But unlike their other processors, there are no royalties for the cortex m0 (Arm is trying to take out the 8/16 bit market).
In a spartan 6 FPGA a cortex m0 can run up to 60 MHz with a simple SoC design, more complex designs drop it down to around 45 to 50 MHz. A NIOS II/e is up to 220 MHz, with the II/f being up to 170 MHz in a cyclone v. But the NIOS II/e only does 0.15 DMIPS/MHz, compared to the cortex m0's 1.03 to 1.04 DMIPS/MHz (this should really be 0.98 to 1.04, but GCC's small-multiply option really makes quite a difference), so you get 50% more DMIPS at a lower operating frequency. Of course, the NIOS II/f gives better performance (1.13 DMIPS/MHz), but takes up more resources.
In terms of resources, the cortex m0 is around 3500 LUTs and 1000 registers, with the NIOS II/e using 1200 LUTs and 900 registers, and the II/f using 2500 LUTs and 1900 registers.
Overall the cortex m0 is quite good in a SoC, but only if you can get away with the lower clock speed (or implement CDC on your peripherals). If you need something small and fast, it is much better to ignore the NIOS II/e and instead go for the PicoRV32 (
https://github.com/cliffordwolf/picorv32), which uses 1400 LUTs and 600 registers (same rough size as the II/e) but gives 0.327 DMIPS/MHz instead of 0.15, and has a maximum frequency in excess of 200 MHz.
Xilinx's microblaze (on minimum area settings) is a bit better than the cortex m0 - it uses roughly the same amount of resources as the NIOS II/e but has around 1.07 DMIPS/MHz, but it is only free on 7 series devices (expensive licenses if you are targeting the spartan 6, although not in the same region as the cortex m0).
Microsemi's use of the cortex m1 on certain FPGAs is a little different - it is provided as a mapped and routed encrypted IP, so it can only fit into a certain place on the FPGA. I haven't used it, but I would imagine this would really hit clock speeds of larger designs as it will interfere with any place and route optimisations.