It comes down to the largest Diesize that the package can accept.
Yes, but it's also marketing. I've asked both Xilinx and Altera at high levels back in the day and they both responded with "because no one wants them".
Me - "Well, have you tried making one to see?"
Them - "Nope, we know no one wants them, there is no market for them."
Even mid level gate count in a usable package would have been a step forward.
A 44pin PLCC is a pretty darn big package at about 16x16mm for example.