AmpHour #181 Low Pin Count High Gate Count FPGAs

[lgbeno]

This message is mostly for Dave @eevblog but there is a very good reason why historically you cannot get a high gate count FPGA in a small or low pin count package. 

It comes down to the largest Diesize that the package can accept.  The logic & fabric alone in a million gate FPGA is larger than what a 6x6QFN can hold therefore a bigger package is going to be required.  You could say that yes, you could only bond out the pads required for your application to save some cost in wirebonding but those large devices like you mentioned in the podcast are most likely flipchip anyway so the cost for pins is fixed unlike in wirebonded packages where it is more variable.

All of that said, as FPGAs move to smaller geometries like 22nm, this dream could become more of a possibility but then at the expense of dropping the core and IO voltages.

[JoeN]

Altera says they will be on the 14nm node soon.  I wonder if they will provide some small packages. 

http://www.altera.com/technology/system-tech/next-gen/process-technologies.html

Intel says that it's 14nm node is nearing production capability and will be producing chips this Q1:

http://www.xbitlabs.com/news/cpu/display/20140120233109_Intel_on_Track_with_Broadwell_Production_in_Q1_Company.html

[mikeselectricstuff]

Screw high gate count, I'd be glad of _ANY_ gate count in a 48 or 64 pin QFP/QFN

[cosmos]

Well if the area of the package is the problem you can get a Spartan 6 i 8x8mm CPG196 (0.5mm pitch) ...
 but soldering it will be nothing like a QFP of course.

[brabus]

Screw high gate count, I'd be glad of _ANY_ gate count in a 48 or 64 pin QFP/QFN

Dear Mike, I once used this puppy: http://www.cs.york.ac.uk/rts/docs/Xilinx-datasource-2003-q1/datasheets/ds091.pdf
Xilinx XC2C32, 32 logic blocks in a comfortable QFP44 package.

What happened, is that the 32 logic blocks were OK for the first revision of the project (a simple latched buffer), but were not enough for the subsequent customer's need (as always, new inputs come when the project is almost finished).
How did I solve the thing? Package on Package: soldering a second QFP44 over the existing one, chaining the pins for JTAG programming, soldering the supplies and finally die drown in a sea of patch wire.

What a rip-off...

[scientist]

This message is mostly for Dave @eevblog but there is a very good reason why historically you cannot get a high gate count FPGA in a small or low pin count package. 

It comes down to the largest Diesize that the package can accept.  The logic & fabric alone in a million gate FPGA is larger than what a 6x6QFN can hold therefore a bigger package is going to be required.  You could say that yes, you could only bond out the pads required for your application to save some cost in wirebonding but those large devices like you mentioned in the podcast are most likely flipchip anyway so the cost for pins is fixed unlike in wirebonded packages where it is more variable.

All of that said, as FPGAs move to smaller geometries like 22nm, this dream could become more of a possibility but then at the expense of dropping the core and IO voltages.

The die in a Spartan6 LX9 is only about 6mm to a side, and I have thermal images to prove it. Tell me that can't be put in a smaller package than a QFP208.

[EEVblog]

It comes down to the largest Diesize that the package can accept.

Yes, but it's also marketing. I've asked both Xilinx and Altera at high levels back in the day and they both responded with "because no one wants them".
Me - "Well, have you tried making one to see?"
Them - "Nope, we know no one wants them, there is no market for them."
Even mid level gate count in a usable package would have been a step forward.
A 44pin PLCC is a pretty darn big package at about 16x16mm for example.

[peter.mitchell]

i wonder if you could get a large FPGA, in an FCPGA , where the pins aren't soldered to the pads, but are actually molded into the epoxy, so you can solder it straight in as a thru-hole...

[andersm]

Yes, but it's also marketing. I've asked both Xilinx and Altera at high levels back in the day and they both responded with "because no one wants them".
Me - "Well, have you tried making one to see?"
Them - "Nope, we know no one wants them, there is no market for them."

Several years ago on Usenet, one Xilinx employee put it slightly differently, namely that their big customers were all about having tons of I/O.

[Bassman59]

Yes, but it's also marketing. I've asked both Xilinx and Altera at high levels back in the day and they both responded with "because no one wants them".
Me - "Well, have you tried making one to see?"
Them - "Nope, we know no one wants them, there is no market for them."

Several years ago on Usenet, one Xilinx employee put it slightly differently, namely that their big customers were all about having tons of I/O.

That would certainly explain why the smallest of the Artix-7 family that you can actually buy is the XC7A100. The 35, 50 and 75 aren't even listed as orderable from DigiKey or Avnet. The first blurbs we got from Xilinx promised a 20, which appears nowhere in current documentation.

And yet Xilinx wonders why users of the Spartan 3AN family haven't migrated to the series 7 parts yet ...