Hi everyone! Thought I would ask this here before I send my design to production.
I have a board that uses a MAX V (5M570Z) CPLD and because my application has become more memory dependent, I am migrating to the LCMXO2-4000HC in order to use the distributed RAM and/or embedded block ram, which should fix my performance issues.
Is there anything out of the ordinary I should consider? I am new to using Lattice parts
The MAX V has two banks, the left bank I connected to the MCU and the right bank to the memory device. For the LCMXO2, which has 5 banks, I connected Bank 0 and 2 to the MCU (and same VCCIO), and BANK 1,3,5 to the memory device (and VCCIO).
I have all hardened protocols connected: JTAG, SPI, I2C, and the dedicated programming pins (PRGMN, INITN, DONE) connected to the MCU.
For clocking, I have 3 input sources: 2 of the MCU's PCK and a 40MHZ MEMS wired like this:
40MHZ MEMS Oscillator = PCLKC0_1
MCU_PCK0 = PCLKC2_0
MCU_PCK1 = PCLKT2_1
But the rest of the clock/pll pins are NC. To future proof my design, is there anything I should connect to them? They are:
L_GPLLT_FB, L_GPLLC_FB, L_GPLLT_IN, L_GPLLC_IN, L_GPLLT_FB, L_GPLLC_FB, L_GPLLT_IN, L_GPLLC_IN
Any advice would be much appreciated!